VLSI Design Automation (Spring 2016)

Announcements

  • [2016/2/20] Welcome to take the "VLSI design automation" course.
  • [2016/3/3]
    • TA for this course is found, and the office hours are set.
    • Reading Chapter 6 of ref [1].
  • [2016/4/22] The lecture on April 25th will be reschedule to 18:00pm @H2-315.

Course Description

The course focuses on the fundamental mathematics, data structures, and algorithms that enable the automatic design of modern very large scale integrated circuits.

The content includes: Introduction to computational Boolean algebra such as binary decision diagram and satisfiability; Two-level and multi-level logic synthesis; Technology mapping; Physical design including partitioning, floorplanning, placement, and routing; Timing analysis; Large-scale optimization heuristics such as simulated annealing.

Logistics

  • Time: Mon./Thurs., 3pm - 4:40pm.

  • Location: H2 - 315

  • Instructor: Pingqiang Zhou (zhoupq@shanghaitech.edu.cn)

    • Office hours: Mon., 1:30 - 2:30pm, or by appointment. Venue: H2-213.

  • TA: Leilei Wang (wangll@shanghaitech.edu.cn).

    • Office hours: Thur., 1:30 - 2:30pm. Venue: H2 - 301.

References

  1. “Electronic Design Automation: Synthesis, Verification, and Test (Systems on Silicon),”  by Laung-Terng Wang, Yao-Wen Chang, and Kwang-Ting Cheng, Morgan Kaufmann Publishing, 2009.

  2. “Logic Synthesis and Verification Algorithms,” by Gary Hachtel and Fabio Somenzi, Springer Publishing,1996.

  3. “VLSI Physical Design Automation,” by Sadiq Sait and Habib Youssef, World Scientific Publishing, 1999.

                                                                                Course Schedule

Week Date Lecture slides Reading materials Assignments
1 Feb 22    
Feb 25      
2 Feb 29 Algorithms [slides]  
Mar 3      
3 Mar 7      
Mar 10 Computational Boolean Algebra [slides]  

1. Programming assignment 1:

  • Due: Mar 24th, 11:59PM.
  • Problem formulation [pdf]
  • Test cases [c499&b15_C]
  • Additional test cases [inputs]
  • STL intro [slides]

2. Written assignment 1:

 
4 Mar 14      
Mar 17      
5 Mar 21 BDD [slides]    
Mar 24      
6 Mar 28 SAT [slides]  

 Programming assignment 2:

  • Due: April 10th, 11:59PM.
  • Problem formulation [pdf]
  • Related files [tarball]
Mar 31 Two-Level Logic Synthesis [slides]  

 
7 April 5 Multi-Level Logic Synthesis [slides]  

1. Reading/hand-on assignment 1: Survey of 3 SAT solvers

  • Oral due: April 14th
  • Written due: April 19th

2. Written assignment 2:

 
April 7 Technology Mapping [slides]    
8 April 11      
April 14  Placement [slides]     
9 April 18      
April 21      
10 April 25

Reading/hand-on assignment 2: Survey of academic placers

  • Oral due: May 16th
  • Written due: May 23th
April 28    

 Programming assignment 3:

  • Due: May 22th, 11:59PM.
  • Problem formulation [pdf]
  • Related files [tarball]
11 May 2      
May 5      
12 May 9      
May 12      
13 May 16      
May 19 Routing [slides]    
14 May 23      
May 26      
15 May 30  Static Timing Analysis [slides]    
June 2    

1. Written assignment 3:

2. Project (due on June 26th)
16 June 6      
June 9      

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

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