Digital  Integrated Circuits II (Spring 2018)


Lecture
  • Time:
    • Wednesday 10:15AM - 11:55AM
    • Friday 10:15AM - 11:55AM
  • Venue: SIST 1D-104.

Course Description

This course is targeted for students who have already taken basic VLSI design classes and would like to learn more about real world challenges in designing high-performance and low-power circuits. Lectures will emphasize on nanoscale CMOS issues such as leakage, variability, robustness, power delivery, interconnect, memory, etc.


 

 

 

 References

  1. J. M. Rabaey, A. Chandrakasan, B. Nikolić, Digital Integrated Circuits - A Design Perspective, 2nd ed., 2003.

  2. N. H. E. Weste and D. Harris, CMOS VLSI Design, 4th ed., Addison Wesley, Reading, MA, 2011.

  3. J. Rabaey, Low Power Design Essentials, Springer 2009.

  4. A. Chandrakasan, W. Bowhill, F. Fox, Design of High-Performance Microprocessor Circuits, Wiley-IEEE, 2000.

 

Course Schedule
Week Date
Topic
Reading
Lecture slides Assignments
1 Feb. 28 IC intro
  • FinFET Talk  [mp4]
  • From sand to chip [mp4]
  • Lec0-part1 [pdf]
  • Lec0-part2 [pdf]
 
Mar. 2 From system to device
  • ASIC design flow [pdf]
  • Lec1-part1 [pdf]
  • Lec1-part2 [pdf]
 
2 Mar. 7 Design metrics  
Mar. 9 Device manufacturing
  • Lec3-part1 [pdf]
  • Lec3-part2 [pdf]

 

 
3 Mar. 14
  • Lab1 [pdf]
    • Due: Mar. 21, 11:59pm
Mar. 16 Transistor models
  • BSIM4 model [link]
  • Lec4-part1 [pdf]
  • Lec4-part2 [pdf]
  • Lec4-part3 [pdf]
  • Lec4-part4 [pdf]

 

 

 
4 Mar. 21
  • HW1 [pdf]
    • Due: Mar. 28, 11:59pm
    • 45nm model files [RAR file]
Mar. 23
5 Mar. 28 Wire models  

 

Mar. 30
  • HW2 [pdf]
    • Due: April 8, in class
  • Lab2 [pdf]
    • Due: April 13, 11:59pm
6 April 4 Inverter
  • Lec6-part1 [pdf]
  • Lec6-part2 [pdf]
  • Lec6-part3 [pdf]
  • Lec6-part4 [pdf]

 

 

 
April 8  
7 April 11

 

April 13 Complementary
CMOS
  • Lec7A-part1 [pdf]
  • Lec7A-part2 [pdf]
  • Lec7A-part3 [pdf]
  • Lec7A-part4 [pdf]

 

8 April 18
  • HW3 [pdf]
    • Due: April 27, in class
April 20

 

9 April 25 Ratioed Logic  
  • Lec7B-part1 [pdf]
  • Lec7B-part2 [pdf]
  • Lec7B-part3 [pdf]
  • HW4 [pdf]
    • Due: May 2, in class
April 27 PT Logic    
10 May 2 Dynamic Logic
May 4 Midterm exam  
  • Solution [pdf]
11 May 9 Adder  
  • Lab3 [pdf]
    • Files [rar]
    • Due: 11:59pm of May 18 (schematic)/May 27 (layout)
May 11  Project proposal due
12 May 16
May 18 Multiplier, mux, decoder, etc.  

Project proposal finalized

13 May 23 Latch and Flip-Flop  

 

 

May 25    
14 May 30 Timing, clock
June 1  
15 June 6  
June  8    
16 June 13 Memory
June  15
  • Take-home exam[pdf]
    • Due: 12pm, 6/22
17 June 20      
June 22    
  • Take-home exam due
18 June 27
June 29      
  • Project report due 23:59, July 1st
  • Report samples [1, 2, 3]