• Lists of current projects:
 
  • System/Architecture Level
    1. ● Energy-efficient communication in heterogeneous multicore chips
    2. ● Energy-efficient power supply in multicore chips
  • CAD/Algorithm Level
    1. ● CAD for reliable and efficient neural network accelerator
    2. ● Security of adversarial examples in deep neural networks
  • Circuit Level
    1. ● Stress issues in TSV based 3D-IC
  • Device Level
    1. ● Device modeling and process diagnosis

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    Goals: Due to massive parallel data processing in DNN models, the performance of current NN accelerators is limited by the communication overhead. Not only the energy consumption but also the clock delay are largely affected by data transmission networks. Therefore, we are targeting to design energy-efficient interconnection networks on-chip which is known as Network-on-Chip (NoC) for NN accelerators. Moreover, we also focus on the co-exploration of NoC and the emerging techniques, such as NoC for the 3D vertical IC, NoC for the RRAM-based accelerator, etc.
     
    Members:
     
    • Wei Gao
    • Xiangwei Cai
    • Yang Li
     
     
       
           
         
    Publications:
     
    1. J. Yin, P. Zhou, S. S. Sapatnekar, and A. Zhai, "Energy-Efficient Time-Division Multiplexed Hybrid-Switched NoC for Heterogeneous Multicore Systems," IEEE International Parallel & Distributed Processing Symposium, pp. 293-303, 2014.
    2. Xiangwei Cai, Jieming Yin, and Pingqiang Zhou, "An orchestrated NoC Prioritization Mechanism for Heterogeneous CPU-GPU Systems," Integration, the VLSI Journal, Vol.65, pp. 344-350, March 2019.
    3. Wei Gao, Zhiliang Qian, and Pingqiang Zhou, "Reliability-and Performance-Driven Mapping for Regular 3D NoCs Using A Novel Latency Model and Simulated Allocation," Integration, the VLSI Journal, Vol.65, pp. 351-361, March 2019.
    4. Wei Gao and Pingqiang Zhou. “Customized high performance and energy-efficiency network-on-chip for AI chips,” IEEE Access, Vol.7, pp. 69434-69446, May 2019.
     
    Goals: DVFS is one of the most effective techniques to reduce power consumption in multicore chips. The variations in the power demands over all the cores in chip can be best met if DVFS is supported by providing multiple levels of Vdd supplies from on-chip voltage regulators (DC-DC converters) that are essential components of the power delivery network. This project studies the design and optimization of SC converters for DVFS in multicore power delivery system that may have multiple power/voltage domains.
     
    Members:
     
    • Leilei Wang
    • Lu Wang
    • Dejia Shang
    • Chengrui Zhang
    • Yuanchen Qu
     
     
       
           
         
    Publications:
     
    1. P. Zhou, V. Mishra, and S. S. Sapatnekar, “Placement optimization of power supply pads based on locality,” DATE, pp. 1655-1660, 2013.
    2. P. Zhou, A. Paul, C. H. Kim, and S. S. Sapatnekar, “Distributed on-chip switched-capacitor DC-DC converters supporting DVFS in multicore systems,” IEEE Transactions on VLSI, vol. 22, no. 9, pp. 1954–1967, 2014.
    3. P. Zhou, “Design and optimization of on-chip voltage regulators for high performance applications,” ICSICT, pp. 1-4, 2014. (Invited)
    4. Leilei Wang and Pingqiang Zhou, “Leakage power reduction in multicore chips via online decap modulation,” CSTIC, pp. 1-3, 2016. (Best Student Paper Award Nomination)
    5. Leilei Wang, Chen Zhuo, and Pingqiang Zhou, “Run-time demand estimation and modulation of on-chip decaps at system level for leakage power reduction in multicore chips,” Integration, the VLSI Journal, Vol.65, pp. 322-330, 2019.
    6. Leilei Wang and Pingqiang Zhou, “An improved leakage-driven runtime decap modulation algorithm for microprocessors,” CSTIC, pp. 1-3, 2018.
    7. Lu Wang, Leilei Wang, Dejia Shang, Chen Zhuo, and Pingqiang Zhou, "Optimization of switched-capacitor DC-DC converters in heterogeneous multicore systems." The Design, Automation, and Test in Europe Conference, 2019. (Acceptance rate: 24%, long presentation).
    8. Leilei Wang, Lu Wang, Chen Zhuo, and Pingqiang Zhou, "Early-Stage Planning of Switched-Capacitor Converters in a Heterogeneous Chip," IEEE Access, vol. 8, pp. 85900–85911, 2020.
    9. Chengrui Zhang and Pingqiang Zhou, "Improved Hierarchical IR Drop Analysis in Homogeneous Circuits," Proceedings of the IEEE International Conference on Solid-State and Integrated Circuit Technology, pp. 1-3, 2020.
    10. Yuanchen Qu and Pingqiang Zhou, "An Improved Design of Hybrid Integrated Voltage Regulator Based on DLDO and SCVR," Proceedings of the IEEE International Conference on Solid-State and Integrated Circuit Technology, pp. 1-3, 2020.
       
    Goals: Resistive random-access memory (ReRAM) is one of the most promising emerging non-volatile memory, featuring high speed, high density and low power. ReRAM-based accelerator chips can achieve better power efficiency and real-time performance for both DNN and neuromorphic computing. Despite these advantages, just like other nano-scale devices in post-CMOS era, ReRAM also faces reliable problems inevitably. When they are considered in the context of accelerator design, VLSI CAD should be adapted. We also focus on design methodology flow from algorithm to architecture exploration, performance prediction of such emerging acceleration.
     
    Members:
     
    • Yu Ma
    • Chenguang Zhang
    • Chengrui Zhang
    • Ziwen Li
     
     

       
           
         
    Publications:
     
    1. Yu Ma, Pingqiang Zhou, "Efficient Techniques for Training the Memristor-based Spiking Neural Networks Targeting Better Speed, Energy and Lifetime," in Proceedings of the IEEE IEEE Asia and South Pacific Design Automation Conference, pp.390-395, 2021.
    2. Chenguang Zhang, Pingqiang Zhou, "A Quantized Training Framework for Robust and Accurate ReRAM-based Neural Network Accelerators," Proceedings of the IEEE Asia and South Pacific Design Automation Conference, pp.43-48, 2021.
       
    Goals: Adversarial examples have greatly threatened neural networks, and the application of neural networks has also been severely restricted. In this project, we study the amplitude characteristics of adversarial perturbations, and defend against adversarial examples based on the image's bit plane.
     
    Members:
     
    • Yuan Liu
    • Jinxin Dong
     
     
       
    Generation of adversarial examples [Goodfellow, Ian, et al., 2014]
       
         
    Publications:
     
    1. Yuan Liu, Pingqiang Zhou, "Defending Against Adversarial Attacks in Deep Learning with Robust Auxiliary Classifiers Utilizing Bit Plane Slicing," in Proceedings of the IEEE Asian Hardware Oriented Security and Trust Symposium, pp.1-4, 2020.
       
    Goals: Three Dimensional Integrated Circuit (3D-IC) can archieve high integration density and fast intra-die connection by stacking the dies vertically in one chip package with the help of the Through Silicon Via (TSV). However, the manufacturing process of TSV will induce thermal stress in the die. The project firstly studies the stress distributions in the whole die. Also, other stress sources in 3D-IC like package componets, strained-Si technology and the Shallow Trench Isolation (STI) will be taken into consideration. Then how the stress influences the transistors as well as the circuits performances are researched.
     
    Members:
     
    • Jindong Zhou
    • Youliang Jing
    • Yuyang Chen
     
     
       

    Structure of 3D-IC [Lu T., 2016]
       
         
    Publications:
     
    1. Jindong Zhou, Youliang Jing and Pingqiang Zhou, "The Study of TSV-Induced and Strained Silicon-Enhanced Stress in 3D-IC," Proceedings of the China Semiconductor Technology International Conference, 2021.
       
    Goals: The integrated circuit (IC) technology has rapidly evolved toward the utilization of complex 3D architecture which enables higher device performance with smaller feature sizes. The 3D nanoscale nature provides great challenges for both IC design and manufacturing. Based on advanced architecture (such as FinFET, GAA, monolithic 3D structure, etc.), we focus on device modeling by traditional BSIM-based method and machine learning approach, aiming at delivering more accurate model to enable high efficient IC design. At the same time, we attempt to utilize advanced analytical methods (such as machine learning, deep learning) to respond to metrology and process diagnosis challenges addressed by advanced process, material, architecture.
     
    Members:
     
    • Huifan Zhang
    • Youliang Jing