Project #1:  Energy-efficient Communication in Heterogeneous Multicore Chips
Goals: Process scaling and the critical reality of stringent power and thermal budgets have driven the growth of multicore systems. Homogeneous multicores consist of arrays of similar cores on the same die, while heterogeneous platforms integrate cores with different capacities, functionalities, or even different instruction set architectures, onto a single die. We aims to develop energy-efficient communication solutions to such heterogeneous systems consists of CPU cores and non-CPU cores (such as AI core and GPU cores).
 
Students:
 
  • Wei Gao
  • Xiangwei Cai
 
 
   
       
     
Publications:
 
1. J. Yin, P. Zhou, S. S. Sapatnekar, and A. Zhai, "Energy-Efficient Time-Division Multiplexed Hybrid-Switched NoC for Heterogeneous Multicore Systems," IEEE International Parallel & Distributed Processing Symposium, pp. 293-303, 2014.
2. X. Cai, J. Yin, and P. Zhou, "An orchestrated NoC Prioritization Mechanism for Heterogeneous CPU-GPU Systems," Integration, the VLSI Journal, 2018. (To appear)
3. W. Gao, Z. Qian, and P. Zhou, "Reliability- and Performance-Driven Mapping for Regular 3D NoCs Using A Novel Latency Model and Simulated Allocation," Integration, the VLSI Journal, 2018. (To appear)
4. W. Gao and P. Zhou. “Customized high performance and energy-efficiency network-on-chip for AI chips,” submitting to IEEE Transactions on CAD.
 
Project #2:  Energy-efficient Power Supply in Multicore Chips
Goals: DVFS is one of the most effective techniques to reduce power consumption in multicore chips. The variations in the power demands over all the cores in chip can be best met if DVFS is supported by providing multiple levels of Vdd supplies from on-chip voltage regulators (DC-DC converters) that are essential components of the power delivery network. This project studies the design and optimization of SC converters for DVFS in multicore power delivery system that may have multiple power/voltage domains.
 
Students:
 
  • Leilei Wang
  • Lu Wang
  • Dejia Shang
 
 
   
       
     
Publications:
 
1. P. Zhou, V. Mishra, and S. S. Sapatnekar, “Placement optimization of power supply pads based on locality,” DATE, pp. 1655-1660, 2013.
2. P. Zhou, A. Paul, C. H. Kim, and S. S. Sapatnekar, “Distributed on-chip switched-capacitor DC-DC converters supporting DVFS in multicore systems,” IEEE Transactions on VLSI, vol. 22, no. 9, pp. 1954–1967, 2014.
3. P. Zhou, “Design and optimization of on-chip voltage regulators for high performance applications,” ICSICT, pp. 1-4, 2014. (Invited)
4. L. Wang and P. Zhou, “Leakage power reduction in multicore chips via online decap modulation,” CSTIC, pp. 1-3, 2016. (Best Student Paper Award Nomination)
5. L. Wang, C. Zhuo, and P. Zhou, “Run-time demand estimation and modulation of on-chip decaps at system level for leakage power reduction in multicore chips,” Integration, the VLSI Journal, 2018. (To appear)
6. L. Wang and P. Zhou, “An improved leakage-driven runtime decap modulation algorithm for microprocessors,” CSTIC, pp. 1-3, 2018.
7. L. Wang, L. Wang, D. Shang, C. Zhuo, and P. Zhou, "Optimization of switched-capacitor DC-DC converters in heterogeneous multicore systems." (Under review).
   
     
Project #3:  Machine Learning for Reliable Power Supply in Multicore Chips
Goals: In modern microprocessor and SoC designs, supply noise margin has been significantly reduced due to the continuously decreasing supply voltage level. On the other hand, with increasing current density, chips may see larger supply noise variations on various spots and from time to time. As a result, chip robustness and reliability are inevitably deteriorated with more frequent supply noise emergencies. In this project, we aims to build a cross-layer framework for spatial and temporal supply noise prediction, using machine learning and statistical methods.
 
Students:
 
  • Xiaochen Liu
  • Yaguang Li
  • Hui Zhao
 
 
   
       
     
Publications:
 
1. X. Liu, S. Sun, P. Zhou, X. Li, and H. Qian, A Statistical Methodology for Noise Sensor Placement and Full-Chip Voltage Map Generation,” DAC, pp. 1-6, 2015.
2. X. Liu, S. Sun, X. Li, H. Qian, and P. Zhou, “Machine learning for noise sensor placement and full-chip voltage emergency detection,” IEEE Transactions on CAD, 36(3):421-434, Sept. 2016.
3. P. Zhou, “Design and CAD of noise sensors for on-die supply voltage emergency detection,” ICSICT, pp. 593-596, 2016. (Invited)
4. Y. Li and P. Zhou, “An outlier detection method and its application to multicore-chip power estimation,” ASICON, pages 460-463, 2017. (Invited)
5. Y. Li, C. Zhuo, and P. Zhou, “A system level framework for on-line supply noise prediction,” DAC, 2018.
6. R. Weng, Y. Li, W. Gao, L. Wang, X. Kou and P. Zhou, “Deep learning for spatial supply noise estimation in a processor chip,” ICSICT, 2018. (Invited)
7. Y. Li, C. Zhuo, and P. Zhou, “A system-level framework for online power and supply noise prediction,” IEEE Transactions on CAD. (To appear)
8. H. Zhao, W. Gao, and P. Zhou, “A black-box data-dependent dynamic power estimation method for FPGA-based accelerators,” submitting to IEEE Transactions on CAD.
   
     
Project #4:  Can Split Manufacturing Prevents Hardware Treojan?
Goals: With the trend of outsourcing fabrication, split manufacturing is regarded as a promising way to both acquire the high-end nodes in untrusted external foundries and protect the design from potential attackers. In this project, we study the security level of split manufacturing under various attacks. We also study the corresponding effective defense methods.
 
Students:
 
  • Zhang Chen
  • Yajun Yang
  • Jun Wen
 
 

[J. Rajendran et al., DATE'13]
   
       
     
Publications:
 
1. Z. Chen, P. Zhou, T. Y. Ho and Y. Jin, "How Secure is Split Manufacturing in Preventing Hardware Trojan?," in Proceedings of the IEEE Asian Hardware Oriented Security and Trust Symposium, pp. 1-6, 2016.
2. Y. Yang, Z. Chen, T. Y. Ho, Y. Jin and P. Zhou, "The Attacks and Defenses Under Split Manufacturing," submitting to IEEE Transactions on CAD.