Selected Publications

 Prof. Zhou's  Google Scholar profile page is here.

Please be aware that although PDF files are provided as a courtesy for the publications listed below, many of them are copyrighted by the corresponding publishers.



Book Chapter
  1. Pingqiang Zhou and Sachin S. Sapatnekar, "3D Placement and Routing,"  in Physical Design for 3D Integrated Circuits, CRC press, December 2015. (Invited)

  2. Pulkit Jain, Pingqiang Zhou, Chris H. Kim, and Sachin S. Sapatnekar, "Thermal and Power Delivery Challenges in 3D ICs," in Three-Dimensional Integrated Circuit Design: EDA, Design and Microarchitectures, Springer, Boston, MA, 2010.

 
Journal
  1. Supervised students are denoted with a '*'.

  2. [TED] Youliang Jing, Jindong Zhou, Pingqiang Zhou, " Parasitic Capacitance Modeling of Si-Bulk FinFET-Based pMOS ,"  IEEE Transactions on Electron Devices. (Early Access)

  3. [Access] Leilei Wang*, Lu Wang*, Cheng Zhuo and Pingqiang Zhou, "Early-Stage Planning of Switched-Capacitor Converters in a Heterogeneous Chip," IEEE Access. Vol. 8, pp. 85900-85911, 2020.

  4. [TOADES] Yajun Yang*, Zhang Chen*, Yuan Liu*, Tsung-Yi Ho, Yier Jin and Pingqiang Zhou, "How Secure is Split Manufacturing in Preventing Hardware Trojan?," ACM Transactions on Design Automation of Electronic Systems. Vol. 25, No. 2, pp. 1-23, 2020.

  5. [TCAD] Yaguang Li*, Cheng Zhuo and Pingqiang Zhou, "A Cross-Layer Framework for Temporal Power and Supply Noise Prediction," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 30, No. 10, pp. 1914-1927, 2019.

  6. [Access] Wei Gao* and Pingqiang Zhou, "Customized high performance and energy-efficient communication networks for AI chips," IEEE Access, Vol. 7, pp. 69434-69446, May 2019.

  7. [Integration] Wei Gao*, Zhiliang Qian and Pingqiang Zhou, "Reliability- and Performance-Driven Mapping for Regular 3D NoCs Using A Novel Latency Model and Simulated Allocation," Integration, the VLSI Journal, Vol. 65, pp. 351-361, March 2019.

  8. [Integration] Xiangwei Cai*, Jieming Yin and Pingqiang Zhou, "An Orchestrated NoC Prioritization Mechanism for Heterogeneous CPU-GPU Systems,"  Integration, the VLSI Journal, Vol. 65, pp. 344-350, March 2019.

  9. [Integration] Leilei Wang*, Cheng Zhuo and Pingqiang Zhou, "Run-time Demand Estimation and Modulation of On-Chip Decaps at System Level for Leakage Power Reduction in Multicore Chips,"  Integration, the VLSI Journal, Vol. 65, pp. 322-330, 2019.

  10. [TCPS] Yang Liu, Xiaoming Chen, Dileep Kadambi, Ajinkya Bari, Xin Li, Shiyan Hu and Pingqiang Zhou, "Dependable Visual Light-Based Indoor Localization with Automatic Anomaly Detection for Location-Based Service of Mobile Cyber-Physical Systems," ACM Transactions on. Cyber-Physical Systems, Vol. 3, No. 1, pp. 1-17, Sept. 2018.

  11. [TCAD] Xiaochen Liu*, Shupeng Sun, Xin Li, Haifeng Qian and Pingqiang Zhou, "Machine Learning for Noise Sensor Placement and Full-Chip Voltage Emergency Detection," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, pp.421-434, September 2016.

  12. [TVLSI] Pingqiang Zhou, Ayan Paul, Chris H. Kim, and Sachin S. Sapatnekar, "Distributed On-Chip Switched-Capacitor DC-DC Converters Supporting DVFS in Multicore Systems," IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol. 22, No. 9, pp.1954-1967, September 2014.

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    [TOADES] Pingqiang Zhou, Ping-Hung Yuh, and Sachin S. Sapatnekar, “Optimized 3D Network-on-Chip Design Using Simulated Allocation,” ACM Transactions on Design Automation of Electronic Systems, Vol.17, No.2, pp.1-19, 2012.

    [JCSC] Yuchun Ma, Qiang Zhou, Pingqiang Zhou, and Xianlong Hong, “Thermal Impacts of Leakage Power in 2D/3D Floorplanning,” Journal of Circuits, Systems, and Computers, Vol.19, No.7, pp.1483-1495, 2010.

    [D&T] Pingqiang Zhou, Karthikk Sridharan, and Sachin S. Sapatnekar, “Power Grid Optimization in 3D Circuits Using MIM and CMOS Decoupling Capacitors,” IEEE Design & Test,  Vol.26, No.5, pp.15-25, 2009.

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Conference/Workshop       Supervised students are denoted with a '*'.
  1. [APCCAS] Yu Ma*, Chengrui Zhang* and Pingqiang Zhou, "Efficient Techniques for Extending Service Time of Memristor-based Neural Networks," Proceedings of IEEE Asia Pacific Conference on Circuits and Systems, pp. 1-4, 2021. (to appear)

  2. [GLSVLSI] Yu Ma*, Linfeng Zheng* and Pingqiang Zhou, "Tolerating Stuck-at Fault and Variation in Resistive Edge Inference Engine via Weight Mapping," Proceedings of the 2021 ACM Great Lakes Symposium on VLSI. pp.1-6, 2021.

  3. [ASP-DAC] Chenguang Zhang* and Pingqiang Zhou, "A Quantized Training Framework for Robust and Accurate ReRAM-based Neural Network Accelerators," Proceedings of the IEEE Asia and South Pacific Design Automation Conference, pp.43-48, 2021.

  4. [ASP-DAC] Yu Ma* and Pingqiang Zhou, "Efficient Techniques for Training the Memristor-based Spiking Neural Networks Targeting Better Speed, Energy and Lifetime," Proceedings of the IEEE Asia and South Pacific Design Automation Conference, pp.390-395, 2021.

  5. [AsianHOST] Yuan Liu* and Pingqiang Zhou, "Defending Against Adversarial Attacks in Deep Learning with Robust Auxiliary Classifiers Utilizing Bit Plane Slicing," Proceedings of the IEEE Asian Hardware Oriented Security and Trust Symposium, pp.1-4, 2020.

  6. [ICSICT] Linfeng Zheng*, Hui Zhao* and Pingqiang Zhou, "An Input-Sensitive Dynamic Power Modeling Methodology for AI Chips in Black-Box Form," Proceedings of the IEEE International Conference on Solid-State and Integrated Circuit Technology, 2020.(Invited)

  7. [ICSICT] Yuanchen Qu* and Pingqiang Zhou, "An Improved Design of Hybrid Integrated Voltage Regulator Based on DLDO and SCVR," Proceedings of the IEEE International Conference on Solid-State and Integrated Circuit Technology, pp.1-3, 2020.

  8. [ICSICT] Chengrui Zhang* and Pingqiang Zhou, "Improved Hierarchical IR Drop Analysis in Homogeneous Circuits," Proceedings of the IEEE International Conference on Solid-State and Integrated Circuit Technology, pp.1-3, 2020.

  9. [ASICON] Yu Ma*, Dingcheng Jia*, Wei Gao* and Pingqiang Zhou, "Addressing Aging Issues in Heterogeneous Three-Dimensional Integrated Circuits,"  Proceedings of the IEEE International Conference on ASIC, pp.1-4, 2019. (Invited)

  10. [ASICON] Yu Ma*, Linfeng Zheng* and Pingqiang Zhou, "CoDRAM: A Novel Near Memory Computing Framework with Computational DRAM,"  Proceedings of the IEEE International Conference on ASIC, pp.1-4, 2019.

  11. [ASICON] Yu Ma*, Dingcheng Jia*, Huifan Zhang*, Ruoyu Wang* and Pingqiang Zhou, "A Compact Memory Structure based on 2T1R against Single-Event Upset in RRAM Arrays," Proceedings of the IEEE International Conference on ASIC, pp.1-4,2019.

  12. [DATE] Lu Wang*, Leilei Wang*, Dejia Shang*, Cheng Zhuo and Pingqiang Zhou, "Optimization of switched-capacitor DC-DC converters in heterogeneous multicore systems." The Design, Automation, and Test in Europe Conference, 2019. (Acceptance rate: 24%, long presentation)

  13. [DAC] Yaguang Li*, Cheng Zhuo and Pingqiang Zhou, "A System-Level Framework for Online Power and Supply Noise Prediction in Processor Chips,"  ACM/EDAC/IEEE Design Automation Conference, 2018. (Poster session)

  14. [PLANS] Jiuxin Zhang* and Pingqiang Zhou, "Integrating low-resolution surveillance camera with smartphone inertial sensors for indoor positioning," in Proceedings of the IEEE/ION Position Location and Navigation Symposium, pp. 410-416, 2018.

  15. [AMS] Yaguang Li*, Cheng Zhuo and Pingqiang Zhou, "A system level framework for online supply noise prediction," in International Workshop on Design Automation for Analog and Mixed-Signal Circuits, 2017.

  16. [ASICON] Yaguang Li*, Pingqiang Zhou, "An Outlier Detection Method and its Application to Multicore-Chip Power Estimation," Proceedings of the IEEE International Conference on ASIC, pp. 460-463, 2017. (Invited)

  17. [AsianHOST] Zhang Chen*, Pingqiang Zhou, Tsung-Yi Ho and Yier Jin, "How Secure is Split Manufacturing in Preventing Hardware Trojan?," in Proceedings of the IEEE Asian Hardware Oriented Security and Trust Symposium, pp. 1-6, 2016.

  18. [CAD/CG] Kai Liao* and Pingqiang Zhou, "A Study about Task-Based DVFS Policy," in Proceedings of the IEEE International Conference on Computer-Aided Design and Computer Graphics, 2016.

  19. [ICSICT] Pingqiang Zhou, "Design and CAD of Noise Sensors for On-Die Supply Voltage Emergency Detection," Proceedings of the IEEE International Conference on Solid-State and Integrated Circuit Technology, pp. 593-596, 2016.  (Invited)

  20. [DAC] Xiaochen Liu*, Shupeng Sun, Pingqiang Zhou, Xin Li and Haifeng Qian, "A Statistical Methodology for Noise Sensor Placement and Full-Chip Voltage Map Generation," Proceedings of the ACM/EDAC/IEEE Design Automation Conference, pp. 1-6, 2015.

  21. [ICSICT] Pingqiang Zhou, "Design and Optimization of On-Chip Voltage Regulators for High Performance Applications," Proceedings of the IEEE International Conference on Solid-State and Integrated Circiut Technology, pp. 1-4, 2014. (Invited)

  22. [IPDPS] Jieming Yin, Pingqiang Zhou, Sachin S. Sapatnekar, and Antonia Zhai, “Energy-Efficient Time-Division Multiplexed Hybrid NoC for Heterogeneous Multicore Systems,” Proceedings of the IEEE International Parallel and Distributed Processing Symposium, pp. 293-303, 2014.

  23. [DATE] Pingqiang Zhou, Vivek Mishra, and Sachin S. Sapatnekar, “Placement Optimization of Power Supply Pads Based on Locality,” The Design, Automation, and Test in Europe Conference, pp. 1655-1660, 2013.

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  25. [ICCAD] Pingqiang Zhou, Bongjin Kim, Wonho Choi, Chris H. Kim, and Sachin S. Sapatnekar, “Optimization of On-Chip Switched-Capacitor DC-DC Converters for High-Performance Applications,” Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, pp. 263-270, 2012.

  26. [ICCAD] Jianxin Fang, Saket Gupta, Sanjay Kumar, Sravan Marella, Vivek Mishra, Pingqiang Zhou, and Sachin Sapatnekar, “Circuit Reliability: From Physics to Architectures (Embedded Tutorial),” Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, pp.243-246, 2012.

  27. [ISLPED] Jieming Yin, Pingqiang Zhou, Anup P. Holey, Sachin S. Sapatnekar, and Antonia Zhai, “Energy Efficient Non-Minimal Path On-chip Interconnection Network for Heterogeneous Systems,”Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design, pp.57-62, 2012.

  28. [CICC] Pingqiang Zhou, Dong Jiao, Chris H. Kim, and Sachin S. Sapatnekar, “Exploration of On-Chip Switched-Capacitor DC-DC Converter for Multicore Processors Using a Distributed Power Delivery Network,”Proceedings of the IEEE Custom Integrated Circuits Conference, pp.1-4, 2011.

  29. [TECHON] Pingqiang Zhou, Jieming Yin, Antonia Zhai, and Sachin S. Sapatnekar, “NoC Design and Performance Optimization,” SRC TECHON, 2011.

  30. [ISLPED] Pingqiang Zhou, Jieming Yin, Antonia Zhai, and Sachin S. Sapatnekar,“NoC Frequency Scaling with Flexible-Pipeline Routers,“ Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design, pp.403-408, 2011.

  31. [ASPDAC] Pingqiang Zhou, Ping-Hung Yuh, and Sachin S. Sapatnekar, “Application-Specific 3D Network-on-Chip Design Using Simulated Allocation,”Proceedings of the Asia-South Pacific Design Automation Conference, pp.517–522, 2010. (Nominated for Best Paper Award)

  32. [ASPDAC] Pingqiang Zhou, Karthikk Sridharan, and Sachin S. Sapatnekar, “Congestion-Aware Power Grid Optimization for 3D Circuits Using MIM and CMOS Decoupling Capacitors,” Proceedings of the Asia-South Pacific Design Automation Conference, pp.179–184, 2009.

  33. [SEMATECH] Pingqiang Zhou, Jie Gu, Pulkit Jain, Chris H. Kim, and Sachin S. Sapatnekar, “Reliable Power Delivery for 3D ICs,” Sematech Workshop on Design and Test Challenges for 3D ICs, 2008.

  34. [ICCAD] Pingqiang Zhou, Yuchun Ma, Zhouyuan Li, Robert P. Dick, Li Shang, Hai Zhou, Xianlong Hong, and Qiang Zhou, “3D-STAF: Scalable Temperature and Leakage Aware Floorplanning for Three-dimensional Integrated Circuits,” Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, pp.590–597, 2007.

  35. [CAD/CG] Pingqiang Zhou, Yuchun Ma,Qiang Zhou, and Xianlong Hong, "Thermal Effects with Leakage Power Considered in 2D/3D Floorplanning," Proceedings of the IEEE International Conference on Computer-Aided Design and Computer Graphics, pp.338–343, 2007.

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