publications

publications by categories in reversed chronological order. generated by jekyll-scholar.

2025

  1. Fast FPGA Accelerator of Graph Cut Algorithm With Threshold Global Relabel and Inertial Push
    Guangyao Yan, Xinzhe Liu, Hui Wang, and 1 more author
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2025
    DOI
  2. QuantTPM: Efficient Mixed-Precision Quantization Framework for Tractable Probabilistic Models
    Shen Zhang, Bin Ning, Guangyao Yan, and 3 more authors
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2025
    DOI
  3. FiDRL: Flexible Invocation-Based Deep Reinforcement Learning for DVFS Scheduling in Embedded Systems
    Jingjin Li, Weixiong Jiang, Yuting He, and 7 more authors
    IEEE Trans. Computers, 2025
    DOI
  4. A Deep Investigation on Stealthy DVFS Fault Injection Attacks at DNN Hardware Accelerators
    Junge Xu, Fan Zhang, Wenguang Jin, and 4 more authors
    IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025
    DOI
  5. RefSCAT: Formal Verification of Logic-Optimized Multipliers via Automated Reference Multiplier Generation and SCA-SAT Synergy
    Rui Li, Lin Li, Heng Yu, and 3 more authors
    IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025
    DOI

2024

  1. eCIMC: A603.1-TOPS/W eDRAM-Based Cryogenic In-Memory Computing Accelerator Supporting Boolean/Convolutional Operations
    Yuhao Shu, Hongtu Zhang, Qi Deng, and 4 more authors
    IEEE J. Solid State Circuits, 2024
    DOI
  2. Fast Constraints Tuning via Transfer Learning and Multiobjective Optimization
    Meng Zhang, Zheng Zhang, Yifan Niu, and 5 more authors
    IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024
    DOI
  3. Modeling and Optimization of XOR Gate Based on Stochastic Thermodynamics
    Xiaoxuan Peng, Xiaohu Ge, and Yajun Ha
    IEEE Trans. Circuits Syst. I Regul. Pap., 2024
    DOI
  4. The Optimization of Aging-aware 8T SRAM for FPGA Configuration Memory
    Yifei Li, Yuxin Zhou, Yuhao Shu, and 2 more authors
    In IEEE International Symposium on Circuits and Systems, ISCAS 2024, Singapore, May 19-22, 2024, 2024
    DOI
  5. EarFDA: A Lightweight and Energy-Efficient Fall Detection Accelerator for Ear-Worn Devices
    Zhaodong Lv, Hao Sun, Yuhao Shu, and 1 more author
    In IEEE International Symposium on Circuits and Systems, ISCAS 2024, Singapore, May 19-22, 2024, 2024
    DOI
  6. Machine Learning with Real-time and Small Footprint Anomaly Detection System for In-Vehicle Gateway
    Yi Wang, Yuanjin Zheng, and Yajun Ha
    In IEEE International Symposium on Circuits and Systems, ISCAS 2024, Singapore, May 19-22, 2024, 2024
    DOI
  7. Machine Learning with Real-time and Small Footprint Anomaly Detection System for In-Vehicle Gateway
    Yi Wang, Yuanjin Zheng, and Yajun Ha
    CoRR, 2024
    DOI

2023

  1. A High-Throughput Full-Dataflow MobileNetv2 Accelerator on Edge FPGA
    Weixiong Jiang, Heng Yu, and Yajun Ha
    IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023
    DOI
  2. AOS: An Automated Overclocking System for High-Performance CNN Accelerator Through Timing Delay Measurement on FPGA
    Weixiong Jiang, Heng Yu, Fupeng Chen, and 1 more author
    IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023
    DOI
  3. Criticality-Aware Negotiation-Driven Scrubbing Scheduling for Reliability Maximization in SRAM-Based FPGAs
    Rui Li, Heng Yu, Lin Li, and 1 more author
    IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023
    DOI
  4. A Recursion and Lock Free GPU-Based Logic Rewriting Framework Exploiting Both Intranode and Internode Parallelism
    Lin Li, Rui Li, and Yajun Ha
    IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023
    DOI
  5. An Energy-Efficient Stream-Based FPGA Implementation of Feature Extraction Algorithm for LiDAR Point Clouds With Effective Local-Search
    Hao Sun, Qi Deng, Xinzhe Liu, and 2 more authors
    IEEE Trans. Circuits Syst. I Regul. Pap., 2023
    DOI
  6. WDVR-RAM: A 0.25-1.2 V, 2.6-76 POPS/W Charge-Domain In-Memory-Computing Binarized CNN Accelerator for Dynamic AIoT Workloads
    Hongtu Zhang, Yuhao Shu, Qi Deng, and 3 more authors
    IEEE Trans. Circuits Syst. I Regul. Pap., 2023
    DOI
  7. HRFF: Hierarchical and Recursive Floorplanning Framework for NoC-Based Scalable Multidie FPGAs
    Jianwen Luo, Xinzhe Liu, Fupeng Chen, and 1 more author
    IEEE Trans. Circuits Syst. I Regul. Pap., 2023
    DOI
  8. Outgoing Editorial
    Yajun Ha
    IEEE Trans. Circuits Syst. II Express Briefs, 2023
    DOI
  9. A Reliable and High-Speed 6T Compute-SRAM Design With Dual-Split-VDD Assist and Bitline Leakage Compensation
    Yuqi Wang, Shen Zhang, Yifei Li, and 3 more authors
    IEEE Trans. Very Large Scale Integr. Syst., 2023
    DOI
  10. A 40nm 0.35V 25MHz Half-Select Disturb-Free Bitinterleaving 10T SRAM With Data-Aware Write-Path
    Yifei Li, Jian Chen, Yuqi Wang, and 3 more authors
    In IEEE Custom Integrated Circuits Conference, CICC 2023, San Antonio, TX, USA, April 23-26, 2023, 2023
    DOI
  11. CIMC: A 603TOPS/W In-Memory-Computing C3T Macro with Boolean/Convolutional Operation for Cryogenic Computing
    Yuhao Shu, Hongtu Zhang, Qi Deng, and 2 more authors
    In IEEE Custom Integrated Circuits Conference, CICC 2023, San Antonio, TX, USA, April 23-26, 2023, 2023
    DOI
  12. Fast FPGA Accelerator of Graph Cut Algorithm with Out-of-order Parallel Execution in Folding Grid Architecture
    Guangyao Yan, Xinzhe Liu, Hui Wang, and 1 more author
    In 60th ACM/IEEE Design Automation Conference, DAC 2023, San Francisco, CA, USA, July 9-13, 2023, 2023
    DOI
  13. An Energy-efficient and Fast KNN Search Accelerator for Large Scale Point Cloud Map
    Yunhao Hu, Hao Sun, Chunxu Guo, and 2 more authors
    In 30th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2023, Istanbul, Turkey, December 4-7, 2023, 2023
    DOI
  14. Data Partition Optimization for High Energy Efficiency by Decoupling Local Dependence in Holographic Video Decoder
    Xinzhe Liu, Jianwen Luo, David Blinder, and 5 more authors
    In 30th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2023, Istanbul, Turkey, December 4-7, 2023, 2023
    DOI
  15. NORB: A Stream-Based and Non-Blocking FPGA Accelerator for ORB Feature Extraction
    Qixing Zhang, Hao Sun, Qi Deng, and 2 more authors
    In 30th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2023, Istanbul, Turkey, December 4-7, 2023, 2023
    DOI
  16. CSDB-eDRAM: A 16Kb Energy-Efficient 4T CSDB Gain Cell eDRAM with over 16.6s Retention Time and 49.23uW/Kb at 4.2K for Cryogenic Computing
    Yuhao Shu, Hongtu Zhang, Hao Sun, and 2 more authors
    In IEEE International Symposium on Circuits and Systems, ISCAS 2023, Monterey, CA, USA, May 21-25, 2023, 2023
    DOI
  17. RPS-KNN: An Ultra-Fast FPGA Accelerator of Range-Projection-Structure K-Nearest-Neighbor Search for LiDAR Odometry in Smart Vehicles
    Jianzhong Xiao, Hao Sun, Qi Deng, and 5 more authors
    In IEEE International Symposium on Circuits and Systems, ISCAS 2023, Monterey, CA, USA, May 21-25, 2023, 2023
    DOI
  18. Cryogenic quasi-static embedded DRAM for energy-efficient compute-in-memory applications
    Yuhao Shu, Hongtu Zhang, Hao Sun, and 9 more authors
    CoRR, 2023
    DOI

2022

  1. Quality Optimization of Adaptive Applications via Deep Reinforcement Learning in Energy Harvesting Edge Devices
    Fupeng Chen, Heng Yu, Weixiong Jiang, and 1 more author
    IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
    DOI
  2. FPGA Accelerator for Real-Time Non-Line-of-Sight Imaging
    Zhengpeng Liao, Deyang Jiang, Xiaochun Liu, and 3 more authors
    IEEE Trans. Circuits Syst. I Regul. Pap., 2022
    DOI
  3. Ultra-Fast FPGA Implementation of Graph Cut Algorithm With Ripple Push and Early Termination
    Guangyao Yan, Xinzhe Liu, Fupeng Chen, and 2 more authors
    IEEE Trans. Circuits Syst. I Regul. Pap., 2022
    DOI
  4. Incoming Editorial
    Yajun Ha
    IEEE Trans. Circuits Syst. II Express Briefs, 2022
    DOI
  5. FODM: A Framework for Accurate Online Delay Measurement Supporting All Timing Paths in FPGA
    Weixiong Jiang, Heng Yu, Hongtu Zhang, and 4 more authors
    IEEE Trans. Very Large Scale Integr. Syst., 2022
    DOI
  6. A Reliable 8T SRAM for High-Speed Searching and Logic-in-Memory Operations
    Jian Chen, Wenfeng Zhao, Yuqi Wang, and 3 more authors
    IEEE Trans. Very Large Scale Integr. Syst., 2022
    DOI
  7. Hierarchical and Recursive Floorplanning Algorithm for NoC-Bascd Scalable Multi-Die FPGAs
    Jianwen Luo, Xinzhe Liu, Fupeng Chen, and 1 more author
    In IEEE Asia Pacific Conference on Circuit and Systems, APCCAS 2022, Shenzhen, China, November 11-13, 2022, 2022
    DOI
  8. WSQ-AdderNet: Efficient Weight Standardization Based Quantized AdderNet FPGA Accelerator Design with High-Density INT8 DSP-LUT Co-Packing Optimization
    Yunxiang Zhang, Biao Sun, Weixiong Jiang, and 3 more authors
    In Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2022, San Diego, California, USA, 30 October 2022 - 3 November 2022, 2022
    DOI
  9. Unified Lightweight Authenticated Encryption for Resource-Constrained Electronic Control Unit
    Chunxu Guo, Yi Wang, Fupeng Chen, and 1 more author
    In 29th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2022, Glasgow, United Kingdom, October 24-26, 2022, 2022
    DOI
  10. An Ultra Energy Efficient Streaming-based FPGA Accelerator for Lightweight Neural Network
    Shaoyi Chen, Zhiqi Zhou, and Yajun Ha
    In IEEE International Symposium on Circuits and Systems, ISCAS 2022, Austin, TX, USA, May 27 - June 1, 2022, 2022
    DOI

2021

  1. Hierarchical topometric representation of 3D robotic maps
    Zhenpeng He, Hao Sun, Jiawei Hou, and 2 more authors
    Auton. Robots, 2021
    DOI
  2. DVFS-Based Quality Maximization for Adaptive Applications With Diminishing Return
    Heng Yu, Yajun Ha, Bharadwaj Veeravalli, and 2 more authors
    IEEE Trans. Computers, 2021
    DOI
  3. Analysis and Optimization Strategies Toward Reliable and High-Speed 6T Compute SRAM
    Jian Chen, Wenfeng Zhao, Yuqi Wang, and 1 more author
    IEEE Trans. Circuits Syst. I Regul. Pap., 2021
    DOI
  4. Guest Editorial Special Issue on the 2021 IEEE International Symposium on Circuits and Systems
    Yajun Ha, and Edoardo Bonizzoni
    IEEE Trans. Circuits Syst. II Express Briefs, 2021
    DOI
  5. A 55nm, 0.4V 5526-TOPS/W Compute-in-Memory Binarized CNN Accelerator for AIoT Applications
    Hongtu Zhang, Yuhao Shu, Weixiong Jiang, and 3 more authors
    IEEE Trans. Circuits Syst. II Express Briefs, 2021
    DOI
  6. Guest Editorial Special Issue on the 2021 ISICAS: A CAS Journal Track Symposium
    Yajun Ha, and Edoardo Bonizzoni
    IEEE Trans. Circuits Syst. II Express Briefs, 2021
    DOI
  7. An Optimized FPGA-Based Real-Time NDT for 3D-LiDAR Localization in Smart Vehicles
    Qi Deng, Hao Sun, Fupeng Chen, and 3 more authors
    IEEE Trans. Circuits Syst. II Express Briefs, 2021
    DOI
  8. Analysis and Design of Reconfigurable Sense Amplifier for Compute SRAM With High-Speed Compute and Normal Read Access
    Jian Chen, Wenfeng Zhao, Yuqi Wang, and 1 more author
    IEEE Trans. Circuits Syst. II Express Briefs, 2021
    DOI
  9. Bitwidth-Optimized Energy-Efficient FFT Design via Scaling Information Propagation
    Xinzhe Liu, Fupeng Chen, Raees Kizhakkumkara Muhamad, and 5 more authors
    In 58th ACM/IEEE Design Automation Conference, DAC 2021, San Francisco, CA, USA, December 5-9, 2021, 2021
    DOI
  10. TAIT: One-Shot Full-Integer Lightweight DNN Quantization via Tunable Activation Imbalance Transfer
    Weixiong Jiang, Heng Yu, Xinzhe Liu, and 3 more authors
    In 58th ACM/IEEE Design Automation Conference, DAC 2021, San Francisco, CA, USA, December 5-9, 2021, 2021
    DOI
  11. A Fault Resistant AES via Input-Output Differential Tables with DPA Awareness
    Yi Wang, Marc Stöttinger, and Yajun Ha
    In IEEE International Symposium on Circuits and Systems, ISCAS 2021, Daegu, South Korea, May 22-28, 2021, 2021
    DOI
  12. CLIF: Cross-Layer Information Fusion for Stereo Matching and its Hardware Implementation
    Fupeng Chen, Xinzhe Liu, Heng Yu, and 1 more author
    In IEEE International Symposium on Circuits and Systems, ISCAS 2021, Daegu, South Korea, May 22-28, 2021, 2021
    DOI
  13. Hierarchical Topometric Representation of 3D Robotic Maps
    Zhenpeng He, Hao Sun, Jiawei Hou, and 2 more authors
    CoRR, 2021

2020

  1. A Universal Method of Linear Approximation With Controllable Error for the Efficient Implementation of Transcendental Functions
    Huaqing Sun, Yuanyong Luo, Yajun Ha, and 4 more authors
    IEEE Trans. Circuits Syst. I Regul. Pap., 2020
    DOI
  2. Guest Editorial Special Issue on the 2020 IEEE International Symposium on Circuits and Systems
    Yajun Ha, and Edoardo Bonizzoni
    IEEE Trans. Circuits Syst. II Express Briefs, 2020
    DOI
  3. Guest Editorial Special Issue on the 2020 ISICAS: A CAS Journal Track Symposium
    Yajun Ha, and Edoardo Bonizzoni
    IEEE Trans. Circuits Syst. II Express Briefs, 2020
    DOI
  4. Efficient FPGA Implementation of K-Nearest-Neighbor Search Algorithm for 3D LIDAR Localization and Mapping in Smart Vehicles
    Hao Sun, Xinzhe Liu, Qi Deng, and 3 more authors
    IEEE Trans. Circuits Syst. II Express Briefs, 2020
    DOI
  5. Quality Estimation and Optimization of Adaptive Stereo Matching Algorithms for Smart Vehicles
    Fupeng Chen, Heng Yu, and Yajun Ha
    ACM Trans. Embed. Comput. Syst., 2020
    DOI
  6. PLAC: Piecewise Linear Approximation Computation for All Nonlinear Unary Functions
    Hongxi Dong, Manzhen Wang, Yuanyong Luo, and 4 more authors
    IEEE Trans. Very Large Scale Integr. Syst., 2020
    DOI
  7. DVFS-Based Scrubbing Scheduling for Reliability Maximization on Parallel Tasks in SRAM-based FPGAs
    Rui Li, Heng Yu, Weixiong Jiang, and 1 more author
    In 57th ACM/IEEE Design Automation Conference, DAC 2020, San Francisco, CA, USA, July 20-24, 2020, 2020
    DOI
  8. An Accurate FPGA Online Delay Monitor Supporting All Timing Paths
    Weixiong Jiang, Rui Li, Heng Yu, and 1 more author
    In IEEE International Symposium on Circuits and Systems, ISCAS 2020, Sevilla, Spain, October 10-21, 2020, 2020
    DOI
  9. Energy-Efficient Arbitrary Precision Multi-Bit Multiplication with Bi-Serial In/Near Memory Computing
    Yuqi Wang, Jian Chen, Yu Pu, and 1 more author
    In IEEE International Symposium on Circuits and Systems, ISCAS 2020, Sevilla, Spain, October 10-21, 2020, 2020
    DOI
  10. Optimization of FPGA Routing Networks with Time-Multiplexed Interconnects
    Ruiqi Luo, Xiaolei Chen, and Yajun Ha
    In 11th IEEE Latin American Symposium on Circuits & Systems, LASCAS 2020, San Jose, Costa Rica, February 25-28, 2020, 2020
    DOI
  11. Vulnerability of Deep Learning Model based Anomaly Detection in Vehicle Network
    Yi Wang, Dan Wei Ming Chia, and Yajun Ha
    In 63rd IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2020, Springfield, MA, USA, August 9-12, 2020, 2020
    DOI

2019

  1. Generalized Hyperbolic CORDIC and Its Logarithmic and Exponential Computation With Arbitrary Fixed Base
    Yuanyong Luo, Yuxuan Wang, Yajun Ha, and 3 more authors
    IEEE Trans. Very Large Scale Integr. Syst., 2019
    DOI
  2. Corrections to "Generalized Hyperbolic CORDIC and Its Logarithmic and Exponential Computation With Arbitrary Fixed Base"
    Yuanyong Luo, Yuxuan Wang, Yajun Ha, and 3 more authors
    IEEE Trans. Very Large Scale Integr. Syst., 2019
    DOI
  3. Area-Efficient Distributed Arithmetic Optimization via Heuristic Decomposition and In-Memroy Computing
    Jian Chen, Wenfeng Zhao, and Yajun Ha
    In 13th IEEE International Conference on ASIC, ASICON 2019, Chongqing, China, October 29 - November 1, 2019, 2019
    DOI
  4. Energy Efficiency Optimization of FPGA-based CNN Accelerators with Full Data Reuse and VFS
    Weixiong Jiang, Heng Yu, Xinzhe Liu, and 1 more author
    In 26th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2019, Genoa, Italy, November 27-29, 2019, 2019
    DOI
  5. Area Efficient Box Filter Acceleration by Parallelizing with Optimized Adder Tree
    Xinzhe Liu, Fupeng Chen, and Yajun Ha
    In 2019 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2019, Miami, FL, USA, July 15-17, 2019, 2019
    DOI
  6. Enabling Fine-Grained Dynamic Voltage and Frequency Scaling in SDSoC
    Weixiong Jiang, Heng Yu, and Yajun Ha
    In 32nd IEEE International System-on-Chip Conference, SOCC 2019, Singapore, September 3-6, 2019, 2019
    DOI
  7. AxC-CS: Approximate Computing for Hardware Efficient Compressed Sensing Encoder Design
    Wenfeng Zhao, Biao Sun, Jian Chen, and 1 more author
    In 32nd IEEE International System-on-Chip Conference, SOCC 2019, Singapore, September 3-6, 2019, 2019
    DOI

2018

  1. A Hardware Pipeline with High Energy and Resource Efficiency for FMM Acceleration
    Tian Huang, Yongxin Zhu, Yajun Ha, and 2 more authors
    ACM Trans. Embed. Comput. Syst., 2018
    DOI
  2. Analytical Two-Level Near Threshold Cache Exploration for Low Power Biomedical Applications
    Yun Liang, Shuo Wang, Tulika Mitra, and 1 more author
    In Advanced Computer Architecture - 12th Conference, ACA 2018, Yingkou, China, August 10-11, 2018, Proceedings, 2018
    DOI

2017

  1. An energy-efficient system on a programmable chip platform for cloud applications
    Xu Wang, Yongxin Zhu, Yajun Ha, and 4 more authors
    J. Syst. Archit., 2017
    DOI
  2. An FPGA-Based Cloud System for Massive ECG Data Analysis
    Xu Wang, Yongxin Zhu, Yajun Ha, and 2 more authors
    IEEE Trans. Circuits Syst. II Express Briefs, 2017
    DOI
  3. A DFA-Resistant and Masked PRESENT with Area Optimization for RFID Applications
    Yi Wang, and Yajun Ha
    ACM Trans. Embed. Comput. Syst., 2017
    DOI
  4. Analysis and design of energy-efficient data-dependent SRAM
    Wenfeng Zhao, Ang Li, Yi Wang, and 1 more author
    In 12th IEEE International Conference on ASIC, ASICON 2017, Guiyang, China, October 25-28, 2017, 2017
    DOI
  5. Quality Optimization of Resilient Applications under Temperature Constraints
    Heng Yu, Yajun Ha, and Jing Wang
    In Proceedings of the Computing Frontiers Conference, CF’17, Siena, Italy, May 15-17, 2017, 2017
    DOI

2016

  1. An Optimized Logarithmic Converter With Equal Distribution of Relative Errors
    Mengyao Zhu, Yajun Ha, Chengcun Gu, and 1 more author
    IEEE Trans. Circuits Syst. II Express Briefs, 2016
    DOI
  2. ParaFRo: A hybrid parallel FPGA router using fine grained synchronization and partitioning
    Chin Hau Hoo, Yajun Ha, and Akash Kumar
    In 26th International Conference on Field Programmable Logic and Applications, FPL 2016, Lausanne, Switzerland, August 29 - September 2, 2016, 2016
    DOI
  3. High throughput and resource efficient AES encryption/decryption for SANs
    Yi Wang, and Yajun Ha
    In IEEE International Symposium on Circuits and Systems, ISCAS 2016, Montréal, QC, Canada, May 22-25, 2016, 2016
    DOI
  4. Unified data authenticated encryption for vehicular communication
    Yi Wang, Jianfeng An, and Yajun Ha
    In IEEE 59th International Midwest Symposium on Circuits and Systems, MWSCAS 2016, Abu Dhabi, United Arab Emirates, October 16-19, 2016, 2016
    DOI
  5. Parallel Discord Discovery
    Tian Huang, Yongxin Zhu, Yishu Mao, and 5 more authors
    In Advances in Knowledge Discovery and Data Mining - 20th Pacific-Asia Conference, PAKDD 2016, Auckland, New Zealand, April 19-22, 2016, Proceedings, Part II, 2016
    DOI

2015

  1. Performance and security-enhanced fuzzy vault scheme based on ridge features for distorted fingerprints
    Thi Hanh Nguyen, Yi Wang, Yajun Ha, and 1 more author
    IET Biom., 2015
    DOI
  2. Correlation ratio based volume image registration on GPUs
    Ang Li, Akash Kumar, Yajun Ha, and 1 more author
    Microprocess. Microsystems, 2015
    DOI
  3. Reconfiguring Three-Dimensional Processor Arrays for Fault-Tolerance: Hardness and Heuristic Algorithms
    Guiyuan Jiang, Jigang Wu, Yajun Ha, and 2 more authors
    IEEE Trans. Computers, 2015
    DOI
  4. A 65-nm 25.1-ns 30.7-fJ Robust Subthreshold Level Shifter With Wide Conversion Range
    Wenfeng Zhao, Anastacia B. Alvarez, and Yajun Ha
    IEEE Trans. Circuits Syst. II Express Briefs, 2015
    DOI
  5. Novel Self-Body-Biasing and Statistical Design for Near-Threshold Circuits With Ultra Energy-Efficient AES as Case Study
    Wenfeng Zhao, Yajun Ha, and Massimo Alioto
    IEEE Trans. Very Large Scale Integr. Syst., 2015
    DOI
  6. Challenges and future trends for embedded security in electric vehicular communications
    Yi Wang, Zhiqian Hong, Jun Li, and 2 more authors
    In 2015 IEEE 11th International Conference on ASIC, ASICON 2015, Chengdu, China, November 3-6, 2015, 2015
    DOI
  7. ParaLaR: A parallel FPGA router based on Lagrangian relaxation
    Chin Hau Hoo, Akash Kumar, and Yajun Ha
    In 25th International Conference on Field Programmable Logic and Applications, FPL 2015, London, United Kingdom, September 2-4, 2015, 2015
    DOI
  8. AES architectures for minimum-energy operation and silicon demonstration in 65nm with lowest energy per encryption
    Wenfeng Zhao, Yajun Ha, and Massimo Alioto
    In 2015 IEEE International Symposium on Circuits and Systems, ISCAS 2015, Lisbon, Portugal, May 24-27, 2015, 2015
    DOI
  9. TRISHUL: A Single-pass Optimal Two-level Inclusive Data Cache Hierarchy Selection Process for Real-time MPSoCs
    Mohammad Shihabul Haque, Akash Kumar, Yajun Ha, and 2 more authors
    CoRR, 2015

2014

  1. A Performance and Area Efficient ASIP for Higher-Order DPA-Resistant AES
    Yi Wang, and Yajun Ha
    IEEE J. Emerg. Sel. Topics Circuits Syst., 2014
    DOI
  2. A Low Active Leakage and High Reliability Phase Change Memory (PCM) Based Non-Volatile FPGA Storage Element
    Kejie Huang, Yajun Ha, Rong Zhao, and 2 more authors
    IEEE Trans. Circuits Syst. I Regul. Pap., 2014
    DOI
  3. A 0.4V 280-nW frequency reference-less nearly all-digital hybrid domain temperature sensor
    Wenfeng Zhao, Rui Pan, Yajun Ha, and 1 more author
    In IEEE Asian Solid-State Circuits Conference, A-SSCC 2014, KaoHsiung, Taiwan, November 10-12, 2014, 2014
    DOI
  4. Thermal-aware frequency scaling for adaptive workloads on heterogeneous MPSoCs
    Heng Yu, Rizwan Syed, and Yajun Ha
    In Design, Automation & Test in Europe Conference & Exhibition, DATE 2014, Dresden, Germany, March 24-28, 2014, 2014
    DOI
  5. FPGA-based high throughput XTS-AES encryption/decryption for storage area network
    Yi Wang, Akash Kumar, and Yajun Ha
    In 2014 International Conference on Field-Programmable Technology, FPT 2014, Shanghai, China, December 10-12, 2014, 2014
    DOI
  6. A heterogeneous platform with GPU and FPGA for power efficient high performance computing
    Qiang Wu, Yajun Ha, Akash Kumar, and 3 more authors
    In 2014 International Symposium on Integrated Circuits (ISIC), Singapore, December 10-12, 2014, 2014
    DOI

2013

  1. Improved chaff point generation for vault scheme in bio-cryptosystems
    Thi Hanh Nguyen, Yi Wang, Yajun Ha, and 1 more author
    IET Biom., 2013
    DOI
  2. Quality-Driven Dynamic Scheduling for Real-Time Adaptive Applications on Multiprocessor Systems
    Heng Yu, Yajun Ha, and Bharadwaj Veeravalli
    IEEE Trans. Computers, 2013
    DOI
  3. FPGA-Based 40.9-Gbits/s Masked AES With Area Optimization for Storage Area Network
    Yi Wang, and Yajun Ha
    IEEE Trans. Circuits Syst. II Express Briefs, 2013
    DOI
  4. TRISHUL: A single-pass optimal two-level inclusive data cache hierarchy selection process for real-time MPSoCs
    Mohammad Shihabul Haque, Akash Kumar, Yajun Ha, and 2 more authors
    In 18th Asia and South Pacific Design Automation Conference, ASP-DAC 2013, Yokohama, Japan, January 22-25, 2013, 2013
    DOI
  5. Dynamic Scheduling of Imprecise-Computation Tasks on Real-Time Embedded Multiprocessors
    Heng Yu, Bharadwaj Veeravalli, Yajun Ha, and 1 more author
    In 16th IEEE International Conference on Computational Science and Engineering, CSE 2013, December 3-5, 2013, Sydney, Australia, 2013
    DOI
  6. High Speed Video Processing Using Fine-Grained Processing on FPGA Platform
    Zhi Ping Ang, Akash Kumar, and Yajun Ha
    In 21st IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, FCCM 2013, Seattle, WA, USA, April 28-30, 2013, 2013
    DOI
  7. A directional coarse-grained power gated FPGA switch box and power gating aware routing algorithm
    Chin Hau Hoo, Yajun Ha, and Akash Kumar
    In 23rd International Conference on Field programmable Logic and Applications, FPL 2013, Porto, Portugal, September 2-4, 2013, 2013
    DOI
  8. Criticality-based routing for FPGAS with reverse body bias switch box architectures
    Wei Ting Loke, Wenfeng Zhao, and Yajun Ha
    In 23rd International Conference on Field programmable Logic and Applications, FPL 2013, Porto, Portugal, September 2-4, 2013, 2013
    DOI
  9. FPGA based Rekeying for cryptographic key management in Storage Area Network
    Yi Wang, and Yajun Ha
    In 23rd International Conference on Field programmable Logic and Applications, FPL 2013, Porto, Portugal, September 2-4, 2013, 2013
    DOI
  10. The architecture and placement algorithm for a uni-directional routing based 3D FPGA
    Junsong Hou, Heng Yu, Yajun Ha, and 1 more author
    In 2013 International Conference on Field-Programmable Technology, FPT 2013, Kyoto, Japan, December 9-11, 2013, 2013
    DOI
  11. sAES: A high throughput and low latency secure cloud storage with pipelined DMA based PCIe interface
    Yongzhen Chen, Miguel Rodel Felipe, Yi Wang, and 3 more authors
    In 2013 International Conference on Field-Programmable Technology, FPT 2013, Kyoto, Japan, December 9-11, 2013, 2013
    DOI
  12. An area-efficient shuffling scheme for AES implementation on FPGA
    Yi Wang, and Yajun Ha
    In 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), Beijing, China, May 19-23, 2013, 2013
    DOI
  13. Robustness-driven energy-efficient ultra-low voltage standard cell design with intra-cell mixed-Vt methodology
    Wenfeng Zhao, Yajun Ha, Chin Hau Hoo, and 1 more author
    In International Symposium on Low Power Electronics and Design (ISLPED), Beijing, China, September 4-6, 2013, 2013
    DOI

2012

  1. A low overhead abstract architecture for FPGA resource management
    Rizwan Syed, Yajun Ha, and Bharadwaj Veeravalli
    SIGARCH Comput. Archit. News, 2012
    DOI
  2. A Routing Architecture for FPGAs with Dual-VT Switch Box and Logic Clusters
    Wei Ting Loke, and Yajun Ha
    In Reconfigurable Computing: Architectures, Tools and Applications - 8th International Symposium, ARC 2012, Hong Kong, China, March 19-23, 2012. Proceedings, 2012
    DOI
  3. Power-aware FPGA technology mapping for programmable-VT architectures (abstract only)
    Wei Ting Loke, and Yajun Ha
    In Proceedings of the ACM/SIGDA 20th International Symposium on Field Programmable Gate Arrays, FPGA 2012, Monterey, California, USA, February 22-24, 2012, 2012
    DOI
  4. Parallel dataflow execution for sequential programs on reconfigurable hybrid MPSoCs
    Chao Wang, Xi Li, Xuehai Zhou, and 1 more author
    In 2012 International Conference on Field-Programmable Technology, FPT 2012, Seoul, Korea (South), December 10-12, 2012, 2012
    DOI
  5. A Power and Cluster-Aware Technology Mapping and Clustering Scheme for Dual-VT FPGAs
    Wei Ting Loke, Yajun Ha, and Wenfeng Zhao
    In 26th IEEE International Parallel and Distributed Processing Symposium Workshops & PhD Forum, IPDPS 2012, Shanghai, China, May 21-25, 2012, 2012
    DOI

2011

  1. A Hilbert curve-based delay fault characterization method for FPGAs
    Wenjuan Zhang, and Yajun Ha
    In International Symposium on Circuits and Systems (ISCAS 2011), May 15-19 2011, Rio de Janeiro, Brazil, 2011
    DOI

2010

  1. An Ultra-Low-Energy Multi-Standard JPEG Co-Processor in 65 nm CMOS With Sub/Near Threshold Supply Voltage
    Yu Pu, José Gyvez, Henk Corporaal, and 1 more author
    IEEE J. Solid State Circuits, 2010
    DOI
  2. Ultra Storage-Efficient Time Digitizer for Pseudorandom Single Photon Counter Implemented on a Field-Programmable Gate Array
    Haiting Tian, Shakith Fernando, Hock Wei Soon, and 4 more authors
    IEEE Trans. Biomed. Circuits Syst., 2010
    DOI
  3. Iterative Probabilistic Performance Prediction for Multi-Application Multiprocessor Systems
    Akash Kumar, Bart Mesman, Henk Corporaal, and 1 more author
    IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010
    DOI
  4. B*-tree based variability-aware floorplanning
    Wenjuan Zhang, Shefali Srivastava, and Yajun Ha
    In IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2010, Kuala Lumpur, Malaysia, December 6-9, 2010, 2010
    DOI
  5. Leakage-aware dynamic scheduling for real-time adaptive applications on multiprocessor systems
    Heng Yu, Bharadwaj Veeravalli, and Yajun Ha
    In Proceedings of the 47th Design Automation Conference, DAC 2010, Anaheim, California, USA, July 13-18, 2010, 2010
    DOI
  6. Mapping real-life applications on run-time reconfigurable NoC-based MPSoC on FPGA
    Amit Kumar Singh, Akash Kumar, Thambipillai Srikanthan, and 1 more author
    In Proceedings of the International Conference on Field-Programmable Technology, FPT 2010, 8-10 December 2010, Tsinghua University, Beijing, China, 2010
    DOI
  7. An area-efficient dynamically reconfigurable Spatial Division Multiplexing network-on-chip with static throughput guarantee
    Zhiyao Joseph Yang, Akash Kumar, and Yajun Ha
    In Proceedings of the International Conference on Field-Programmable Technology, FPT 2010, 8-10 December 2010, Tsinghua University, Beijing, China, 2010
    DOI
  8. Communication-aware application mapping and scheduling for NoC-based MPSoCs
    Heng Yu, Yajun Ha, and Bharadwaj Veeravalli
    In International Symposium on Circuits and Systems (ISCAS 2010), May 30 - June 2, 2010, Paris, France, 2010
    DOI
  9. Performance-cost analyses software for H.264 Forward/Inverse Integer Transform
    Trang T. T. Do, Thinh M. Le, Binh P. Nguyen, and 1 more author
    In Proceedings of the 21st IEEE International Symposium on Rapid System Prototyping, RSP 2010, Fairfax, VA, USA, 8-11 June, 2010, 2010
    DOI
  10. Proceedings of the International Conference on Field-Programmable Technology, FPT 2010, 8-10 December 2010, Tsinghua University, Beijing, China
    2010
  11. The Optimization of Interconnection Networks in FPGAs
    Xiaolei Chen, and Yajun Ha
    In Dynamically Reconfigurable Architectures, 11.07. - 16.07.2010, 2010

2009

  1. An optimized design for serial-parallel finite field multiplication over \emphGF(2\(^\mbox\emphm\)) based on all-one polynomials
    Pramod Kumar Meher, Yajun Ha, and Chiou-Yng Lee
    In Proceedings of the 14th Asia South Pacific Design Automation Conference, ASP-DAC 2009, Yokohama, Japan, January 19-22, 2009, 2009
    DOI
  2. A Multi-Application Mapping Framework for Network-on-Chip Based MPSoC: An FPGA Implementation Case Study
    Guolei Zhu, Heng Yu, Yajun Ha, and 1 more author
    In Proceedings of the 2009 International Conference on Engineering of Reconfigurable Systems & Algorithms, ERSA 2009, July 13-16, 2009, Las Vegas Nevada, USA, 2009
  3. sFPGA2 - A scalable GALS FPGA architecture and design methodology
    Rizwan Syed, Xiaolei Chen, Yajun Ha, and 1 more author
    In 19th International Conference on Field Programmable Logic and Applications, FPL 2009, August 31 - September 2, 2009, Prague, Czech Republic, 2009
    DOI
  4. An ultra-low-energy/frame multi-standard JPEG co-processor in 65nm CMOS with sub/near-threshold power supply
    Yu Pu, José Gyvez, Henk Corporaal, and 1 more author
    In IEEE International Solid-State Circuits Conference, ISSCC 2009, Digest of Technical Papers, San Francisco, CA, USA, 8-12 February, 2009, 2009
    DOI

2008

  1. Analyzing composability of applications on MPSoC platforms
    Akash Kumar, Bart Mesman, Bart D. Theelen, and 2 more authors
    J. Syst. Archit., 2008
    DOI
  2. Interference-Minimized Multipath Routing with Congestion Control in Wireless Sensor Network for High-Rate Streaming
    Jenn-Yue Teo, Yajun Ha, and Chen-Khong Tham
    IEEE Trans. Mob. Comput., 2008
    DOI
  3. Multiprocessor systems synthesis for multiple use-cases of multiple applications on FPGA
    Akash Kumar, Shakith Fernando, Yajun Ha, and 2 more authors
    ACM Trans. Design Autom. Electr. Syst., 2008
    DOI
  4. Statistical noise margin estimation for sub-threshold combinational circuits
    Yu Pu, José Gyvez, Henk Corporaal, and 1 more author
    In Proceedings of the 13th Asia South Pacific Design Automation Conference, ASP-DAC 2008, Seoul, Korea, January 21-24, 2008, 2008
    DOI
  5. Dynamic scheduling of imprecise-computation tasks in maximizing QoS under energy constraints for embedded systems
    Heng Yu, Bharadwaj Veeravalli, and Yajun Ha
    In Proceedings of the 13th Asia South Pacific Design Automation Conference, ASP-DAC 2008, Seoul, Korea, January 21-24, 2008, 2008
    DOI
  6. An Area-Efficient Timing-Driven Routing Algorithm for Scalable FPGAs with Time-Multiplexed Interconnects
    Hanyu Liu, Xiaolei Chen, and Yajun Ha
    In 16th IEEE International Symposium on Field-Programmable Custom Computing Machines, FCCM 2008, 14-15 April 2008, Stanford, Palo Alto, California, USA, 2008
    DOI
  7. sFPGA - A scalable switch based FPGA architecture and design methodology
    Shakith Fernando, Xiaolei Chen, and Yajun Ha
    In FPL 2008, International Conference on Field Programmable Logic and Applications, Heidelberg, Germany, 8-10 September 2008, 2008
    DOI
  8. Design of a high speed pseudo-random bit sequence based time resolved single photon counter on FPGA
    Haiting Tian, Shakith Fernando, Hock Wei Soon, and 2 more authors
    In FPL 2008, International Conference on Field Programmable Logic and Applications, Heidelberg, Germany, 8-10 September 2008, 2008
    DOI
  9. An architecture and timing-driven routing algorithm for area-efficient FPGAs with time-multiplexed interconnects
    Hanyu Liu, Xiaolei Chen, and Yajun Ha
    In FPL 2008, International Conference on Field Programmable Logic and Applications, Heidelberg, Germany, 8-10 September 2008, 2008
    DOI
  10. A low overhead fault tolerant FPGA with new connection box
    Fujie Wong, and Yajun Ha
    In FPL 2008, International Conference on Field Programmable Logic and Applications, Heidelberg, Germany, 8-10 September 2008, 2008
    DOI
  11. Tighter WCET analysis of input dependent programs with classified-cache memory architecture
    Yanhui Li, Shakith Fernando, Heng Yu, and 3 more authors
    In 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008, St. Julien’s, Malta, August 31 2008-September 3, 2008, 2008
    DOI

2007

  1. A Probabilistic Approach to Model Resource Contention for Performance Estimation of Multi-featured Media Devices
    Akash Kumar, Bart Mesman, Henk Corporaal, and 2 more authors
    In Proceedings of the 44th Design Automation Conference, DAC 2007, San Diego, CA, USA, June 4-8, 2007, 2007
    DOI
  2. Multi-processor System-level Synthesis for Multiple Applications on Platform FPGA
    Akash Kumar, Shakith Fernando, Yajun Ha, and 2 more authors
    In FPL 2007, International Conference on Field Programmable Logic and Applications, Amsterdam, The Netherlands, 27-29 August 2007, 2007
    DOI
  3. Fast and Accurate Interval-Based Timing Estimator for Variability-Aware FPGA Physical Synthesis Tools
    Chee Sing Lee, Wei Ting Loke, Wenjuan Zhang, and 1 more author
    In FPL 2007, International Conference on Field Programmable Logic and Applications, Amsterdam, The Netherlands, 27-29 August 2007, 2007
    DOI
  4. V\(_\mboxt\)balancing and device sizing towards high yield of sub-threshold static logic gates
    Yu Pu, José Gyvez, Henk Corporaal, and 1 more author
    In Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007, Portland, OR, USA, August 27-29, 2007, 2007
    DOI

2006

  1. An automated, efficient and static bit-width optimization methodology towards maximum bit-width-to-error tradeoff with affine arithmetic model
    Yu Pu, and Yajun Ha
    In Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, Yokohama, Japan, January 24-27, 2006, 2006
    DOI
  2. Global Analysis of Resource Arbitration for MPSoC
    Akash Kumar, Bart Mesman, Henk Corporaal, and 2 more authors
    In Ninth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2006), 30 August - 1 September 2006, Dubrovnik, Croatia, 2006
    DOI
  3. Resource Manager for Non-preemptive Heterogeneous Multiprocessor System-on-chip
    Akash Kumar, Bart Mesman, Bart D. Theelen, and 2 more authors
    In Proceedings of the 2006 4th Workshop on Embedded Systems for Real-Time Multimedia, ESTIMedia 2006, October 26-27, 2006, Seoul, Korea, conjunction with CODES+ISSS 2006, 2006
    DOI

2005

  1. Design of Seamless Protocol Switching Layer for Voice Over Internet Protocol (Voip) That Switches Between Bluetooth and Ieee 802.11
    Yung Han Tan, Arun Krishnan Thampi, Daley Joseph Sebastian, and 1 more author
    Int. J. Softw. Eng. Knowl. Eng., 2005
    DOI
  2. An Embedded System to Support Tele-Medical Activity
    Jia Hui Ng, Chaur Lih Tan, and Yajun Ha
    Int. J. Softw. Eng. Knowl. Eng., 2005
    DOI
  3. Design of Networked Reconfigurable Encryption Engine
    Shakith Fernando, and Yajun Ha
    In 13th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2005), 17-20 April 2005, Napa, CA, USA, Proceedings, 2005
    DOI

2002

  1. Building a Virtual Framework for Networked Reconfigurable Hardware and Software Objects
    Yajun Ha, Serge Vernalde, Patrick Schaumont, and 3 more authors
    J. Supercomput., 2002
    DOI
  2. Adding Hardware Support to the HotSpot Virtual Machine for Domain Specific Applications
    Yajun Ha, Radovan Hipik, Serge Vernalde, and 4 more authors
    In Field-Programmable Logic and Applications, Reconfigurable Computing Is Going Mainstream, 12th International Conference, FPL 2002, Montpellier, France, September 2-4, 2002, Proceedings, 2002
    DOI

2001

  1. Virtual Java/FPGA interface for networked reconfiguration
    Yajun Ha, Geert Vanmeerbeeck, Patrick Schaumont, and 4 more authors
    In Proceedings of ASP-DAC 2001, Asia and South Pacific Design Automation Conference 2001, January 30-February 2, 2001, Yokohama, Japan, 2001
    DOI
  2. A SW/HW Interface API for Java/FPGA Co-Designed Applets
    Yajun Ha, Patrick Schaumont, Serge Vernalde, and 3 more authors
    In The 9th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, FCCM 2001, Rohnert Park, California, USA, April 29 - May 2, 2001, 2001
    DOI
  3. Development of a Design Framework for Platform-Independent Networked Reconfiguration of Software and Hardware
    Yajun Ha, Bingfeng Mei, Patrick Schaumont, and 3 more authors
    In Field-Programmable Logic and Applications, 11th International Conference, FPL 2001, Belfast, Northern Ireland, UK, August 27-29, 2001, Proceedings, 2001
    DOI

2000

  1. Building a Virtual Framework for Networked Reconfigurable Hardware and Software Objects
    Yajun Ha, Serge Vernalde, Patrick Schaumont, and 2 more authors
    In Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, PDPTA 2000, June 24-29, 2000, Las Vegas, Nevada, USA, 2000
  2. A Hardware Virtual Machine for the Networked Reconfiguration
    Yajun Ha, Patrick Schaumont, Marc Engels, and 4 more authors
    In Proceedings of the 11th IEEE International Workshop on Rapid System Prototyping (RSP 2000), Paris, France, June 21-23, 2000, 2000
    DOI

1999

  1. Low-voltage high driving capability CMOS buffer used in MEMS interface circuits
    Yajun Ha, M. F. Li, and Ai Qun Liu
    In 6th IEEE International Conference on Electronics, Circuits and Systems, ICECS 1999, Pafos, Cyprus, September 5-8, 1999, 1999
    DOI