Lab9: Multi-Issue Processors

Getting Started

Download the files for Lab9 first.

Compare a single-issue processor with a simple in-order two-issue processor. In this lab, the wider machine may issue up to two adjacent instructions per cycle, in program order.

Datapath Model

Use the following simplified in-order two-issue model. The pairing logic checks only inst1 and the adjacent inst2. If the pair is legal, both issue in the same cycle. Otherwise only inst1 issues. Either issue slot may hold the one memory operation, but both slots share one LSU path. Branches issue alone.

Multi-issue datapath

Tasks

Inspect examples/pairing_examples.txt, then complete can_pair(inst1, inst2) in code/can_pair.c using only the pairing rules below. Do not search ahead or reorder instructions.

For simplicity this lab features multi-issue blocking (no pipelining) model, so you don't have to consider the forwarding mechanisms shown in our lecture slides.

Besides the obvious data hazards, you need to consider the following rules due to the machine model constraint:

A pair of instructions cannot issue together if either instruction is a branch (branch prediction not considered)
or both are memory operations (there is only one memory slot and LSU path).

Check

Build and run the checks:

gcc -std=c11 -Wall -Wextra -pedantic \
    code/can_pair.c code/check_can_pair.c \
    -o code/check_can_pair
./code/check_can_pair

The check is expected to fail before you complete the TODOs.

Experiments

Run each trace with issue width 1 and issue width 2:

./sim --width 1 traces/arith.trace
./sim --width 2 traces/arith.trace

./sim --width 1 traces/memory.trace
./sim --width 2 traces/memory.trace

./sim --width 1 traces/mixed.trace
./sim --width 2 traces/mixed.trace

Record the results:

Trace	Width	Instructions	Cycles	IPC	Unused issue slots	Blocked pairs
`arith.trace`	1
`arith.trace`	2
`memory.trace`	1
`memory.trace`	2
`mixed.trace`	1
`mixed.trace`	2

Compute speedup:

speedup = width-1 cycles / width-2 cycles

Trace	Width-1 cycles	Width-2 cycles	Speedup
`arith.trace`
`memory.trace`
`mixed.trace`

Questions

Answer briefly, using evidence from your runs.

Show one pair of instructions from the warm-up examples that can issue together. Why is it allowed?
Show one pair of instructions blocked by a RAW dependency. Which register causes the dependency?
Show one pair of instructions blocked by a structural hazard or branch rule. Which rule applies?
Which trace has the highest IPC with width 2? What pattern helps it?
Which trace has the lowest speedup? Use blocked pairs or unused slots to explain why.
Why is the two-issue machine faster than the single-issue machine on some traces?
Why is the measured speedup less than the ideal 2x?
If the issue width increased again, would every trace keep speeding up? Explain using your results.

📋 目录