Project 2.2: Qin110 - RV32I CPU (pipelined)

Computer Architecture I @ ShanghaiTech University

Background

The 110th civilization was destroyed in the gravitational superposition of "Three Suns Aligning". This civilization had evolved to the single-cycle processor era.

As the world tears apart, Von Neumann floats in the vacuum beside Qin Shi Huang, shouting desperately, but no sound escapes, only a line of tiny subtitle: "...I've got it! Split the processor into three stages! Pipelining! The processor could be several times faster!"

After an eternity, life and civilization restart once more in the unpredictable Three-Body world.

In the 219th civilization, once again, you are summoned to lead the design of the great processor Qin110. But this time, you will build a pipelined processor, and you will make it fast.

Please complete your design carefully. Faulty hardware will result in the designer being "repaired".

Introduction

In this project, you need to design a three-stage pipelined processor that supports the RV32I subset. Building upon your single-cycle design from Project 2.1, you will introduce pipeline registers and handle hazards to achieve higher throughput.

You may complete your design using either Logisim or SpinalHDL. You only need to choose one implementation path to finish Project 2.2. This document focuses on the CPU knowledge shared by both implementation paths.

SpinalHDL is a more advanced language than Verilog and VHDL. For beginners, using SpinalHDL makes it easier to master hardware design. In fact, a significant portion of the difficulty in hardware design comes not from hardware itself, but from poorly designed languages like Verilog and VHDL.

GitHub Classroom

Choose exactly one of the following GitHub Classroom assignments:

Logisim version: https://classroom.github.com/a/fUp-i8PW
SpinalHDL version: https://classroom.github.com/a/oUeT61rv

RV32I Instruction

The required instructions are the same as Project 2.1. You have to support following instructions:

add
sub
and
slt
addi
andi
slti
lb
lw
jalr
sb
sw
beq
blt
jal
lui
auipc

You are also encouraged to implement the full RV32I instruction set. Here are the RV32I instruction formats:

Pipeline Microarchitecture

The following figure shows the classic five-stage pipelined RISC-V processor datapath, including pipeline registers and hazard handling logic.

Stage Fetch
Stage Decode
Stage Execute
Stage Memory
Stage Writeback

However, in this project, you are required to implement a much simpler three-stage pipeline, which is divided into:

Stage 1: Fetch
Stage 2: Decode
Stage 3: Execute + Memory + Writeback

You may design your own microarchitecture, but your processor must preserve architectural behavior. The three-stage requirement means that instructions should flow through pipeline registers rather than execute as a single-cycle processor.

Hazards

Pipelining introduces hazards that must be handled to ensure correct execution.

Data Hazard: Forwarding

If a following instruction requires an ALU result that has not been written back yet, a data hazard occurs.

Data hazards caused by ALU can be solved by forwarding:

When delta cycle = 1: forward from stage M to stage E.
When delta cycle = 2: forward from stage W to stage E.
When delta cycle >= 3: no forwarding is required. However, you have to bypass the rd to rs1 or rs2 inside REGFILE. If you read what you write, simply bypass the write data to read data.

In the three-stage pipeline required by this project, execute, memory, and writeback are in the same stage, so no forwarding is required.

You only have to implement REGFILE bypass.

Data Hazard: Stalling

If a following instruction requires a MEM result that has not been written back yet, a data hazard occurs.

Data hazards caused by MEM must be solved by stalling when delta cycle = 1 in a classic five-stage pipeline.

In the three-stage pipeline required by this project, execute, memory, and writeback are in the same stage, so no stalling is required.

Control Hazard: Flushing

When a branch is taken, instructions that were fetched while the branch was being resolved must be flushed from the pipeline. You have to replace the wrong instructions in F/D and the wrong control signals in D/E with harmless bubbles, such as nop and nop's control signals.

In the three-stage pipeline required by this project, flushing is required.

Submission

Submit exactly one implementation path to Gradescope:

If you choose Logisim, submit the Logisim version repository.
If you choose SpinalHDL, submit the SpinalHDL version repository.

Do not submit both versions. Your final score for Project 2.2 is based on the implementation path you choose.

The following TA(s) are responsible for this lab: Chaofan Li <lichf2025@shanghaitech.edu.cn>, Yuxuan Li <liyx22025@shanghaitech.edu.cn>

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