Yajun Ha
Professor @ ShanghaiTech University

Research Interests
- FPGA architectures, tools, and applications
- Ultra-low power circuits and systems
- Embedded system design and methodology for applications in hardware security, smart vehicles and machine learning
Current Positions
Yajun Ha is a distinguished professor at ShanghaiTech University, recognized for his leadership and contributions in academia and research. His key roles and achievements include:
- Professor (Tenured), School of Information Science and Technology, ShanghaiTech University.
- Winner, National Natural Science Foundation of China’s Research Fund for International Senior Scientists and Key International (Regional) Joint Research Program.
- Director, Shanghai Engineering Research Center of Energy Efficient and Custom AI IC.
- Director, PMICC Center and Academic Committee.
- Deputy Director, Teacher Recruitment Committee.
Professional Activities and Services
Prof. Yajun Ha has consistently dedicated himself to making significant contributions to the field of circuits and systems. His key contributions include:
Editorial Roles
- Editor-in-Chief, IEEE Transactions on Circuits and Systems II: Express Briefs (2022–2023).
- Associate Editor-in-Chief, IEEE Transactions on Circuits and Systems II: Express Briefs (2020–2021).
- Associate Editor, IEEE Transactions on Circuits and Systems I: Regular Papers (2016–2019).
- Associate Editor, IEEE Transactions on Circuits and Systems II: Express Briefs (2011–2013).
- Associate Editor, IEEE Transactions on Very Large Scale Integration (VLSI) Systems (2013–2014).
- Associate Editor, Journal of Low Power Electronics (since 2009).
Conference Leadership
- TPC Co-Chair, ISICAS 2020.
- General Co-Chair, ASP-DAC 2014.
- Program Co-Chair, FPT 2010 and FPT 2013.
- Chair, Singapore Chapter of the IEEE Circuits and Systems (CAS) Society (2011–2012).
- Member, ASP-DAC Steering Committee.
- Member, IEEE CAS VLSI and Applications Technical Committee.
Program Committee Member
- Served on program committees for renowned conferences, including DAC, DATE, ASP-DAC, FPGA, FPL, and FPT.
Past Experience and Education
Previous Academic and Professional Roles
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Co-Director & Scientist
I2R-BYD Joint Lab, Institute for Infocomm Research
Agency for Science, Technology and Research, Singapore (Jan. 2014 – Jan. 2017) -
Adjunct Associate Professor
Department of Electrical and Computer Engineering, National University of Singapore (Jan. 2014 – Jan. 2017) -
Assistant Professor
Department of Electrical and Computer Engineering, National University of Singapore (Mar. 2004 – Dec. 2013) -
Affiliate Researcher
Design Technology Division, IMEC, Belgium (Jan. 1999 – Feb. 2004) -
Graduate Research Assistant
Department of Electrical Engineering, National University of Singapore (Jul. 1997 – Jan. 1999) -
Other Professional Experiences
Research Assistant, Department of Electrical Engineering, National University of Singapore (Aug. 1996 – Jun. 1997)
Education
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Ph.D., Electrical Engineering
Katholieke Universiteit Leuven, Belgium (2004) -
M.Eng., Electrical Engineering
National University of Singapore, Singapore (2000) -
B.S., Electrical Engineering
Zhejiang University, Zhejiang, China (1996)
Research Grants
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National Natural Science Fund of China, Joint Fund Project (国自然联合基金项目)
Key Technology Research on Expandable FPGA Architecture and Tools Based on Memristor In-Store Computing
Duration & Funding: 2025.01–2028.01, RMB 2,560,000
Status & Role: ● Ongoing, Principal Investigator (Prof. Yajun Ha) -
National Natural Science Fund of China, International (Regional) Cooperation & Exchange Program (国自然重点国际 (地区) 合作项目)
Research of Key Technologies for Integrated Circuit Reliability Aware Task
Duration & Funding: 2023.01–2027.12, RMB 2,520,000
Status & Role: ● Ongoing, Principal Investigator (Prof. Yajun Ha) -
National Natural Science Fund of China, Research Fund for International Senior Scientists (国自然外国资深学者项目)
Energy Efficient Circuits and Systems for Edge Intelligent Computing
Duration & Funding: 2022.01–2023.12, RMB 1,600,000
Status & Role: ● Completed, Principal Investigator (Prof. Yajun Ha) -
National Natural Science Fund of China, General Program (国自然面上项目)
Key Technology Research on Ultra-Low-Power Sub/Near-Threshold FPGAs
Duration & Funding: 2021.01–2024.12, RMB 590,000
Status & Role: ● Completed, Principal Investigator (Prof. Yajun Ha) -
Shanghai Science and Technology Committee
Shanghai Engineering Research Center of Energy Efficient and Custom AI IC
Duration & Funding: 2021.01–2022.12, RMB 2,000,000 (conditional)
Status & Role: ● Completed, Principal Investigator (Prof. Yajun Ha) -
Shanghai Municipal Science and Technology Commission, Shanghai Natural Science Foundation General Project
Research and Development of Scalable FPGA Architecture and Design Tools Based on Network-on-Chip
Duration & Funding: 2020.07–2023.06, RMB 200,000
Status & Role: ● Completed, Principal Investigator (Prof. Yajun Ha) -
Shanghai Science and Technology Committee
Research of Scalable FPGA Architecture and EDA Tools based on Network-on-Chip
Duration & Funding: 2020.07–2023.06, RMB 200,000
Status & Role: ● Completed, Principal Investigator (Prof. Yajun Ha) -
Research Grant from Aerospace Information Research Institute, Chinese Academy of Science
Research of IP in Field Programmable Neural Network IC Chip
Duration & Funding: 2020.10–2021.04, RMB 300,000
Status & Role: ● Completed, Principal Investigator (Prof. Yajun Ha) -
Shanghai Science and Technology Committee
Research and Development of IC for CMOS Image Sensors
Duration & Funding: 2019.09–2022.08, RMB 2,400,000
Status & Role: ● Completed, Co-Principal Investigator (Prof. Yajun Ha) -
Industry Grant from Voyagerauto Ltd
Energy-efficient High Precision Localization with Sensor Fusion
Duration & Funding: 2019.03–2020.03, RMB 300,000
Status & Role: ● Completed, Principal Investigator (Prof. Yajun Ha) -
Open Research Grant from National Key Lab on IC Design, Ministry of Education, China
Ultra Low Power FPGA
Duration & Funding: 2018.07–2019.12, RMB 100,000
Status & Role: ● Completed, Principal Investigator (Prof. Yajun Ha) -
Start-Up Grant from ShanghaiTech University
Intelligent Hardware Design Framework
Duration & Funding: 2017.01–2021.01, RMB 5,000,000
Status & Role: ● Completed, Principal Investigator (Prof. Yajun Ha) -
Industry Grant from BYD
Autonomous Electric Vehicle Technologies
Duration & Funding: 2013.11–2019.10, SGD 36,000,000
Status & Role: ● Completed, Co-Principal Investigator (Prof. Yajun Ha) -
Singapore A*Star Grant
A Power-Efficient Heterogeneous Architecture and Run-Time Manager for Data Center Servers
Duration & Funding: 2011.08–2013.04, SGD 876,813
Status & Role: ● Completed, Principal Investigator (Prof. Yajun Ha) -
Singapore A*Star Grant
Secured Large Scale Shared Storage System
Duration & Funding: 2011.08–2014.07, SGD 709,092 (out of total SGD 1,815,515)
Status & Role: ● Completed, NUS Principal Investigator (Prof. Yajun Ha) -
A*Star Fund
Pseudo-Random Single Photon Counting for Time-Resolved Optical Spectroscopy and Imaging
Duration & Funding: 2006.07–2009.12, SGD 635,140
Status & Role: ● Completed, Co-Principal Investigator (Prof. Yajun Ha) -
ARF Fund
Global Virtual Machine
Duration & Funding: 2004.01–2008.01, SGD 92,365
Status & Role: ● Completed, Co-Principal Investigator (Prof. Yajun Ha) -
ARF Fund
Networked Reconfigurable Embedded Systems
Duration & Funding: 2004.11–2007.11, SGD 97,789
Status & Role: ● Completed, Principal Investigator (Prof. Yajun Ha)
Awards and Honors
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Best Paper Award
2022 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)
Jianwen Luo, Xinzhe Liu, Fupeng Chen, Yajun Ha, “Hierarchical and Recursive Floorplanning Algorithm for NoC-Based Scalable Multi-Die FPGAs” (2022). -
EDAthon 2021 Champion
2021 IEEE CEDA Hong Kong Chapter
Rui Li, Lin Li, Yajun Ha (2021). -
First Place, DAC 2021 System Design Contest
2021 Design Automation Conference
Zhiqi Zhou, Shaoyi Chen, Weixiong Jiang, Songyang Zhang, Qi Deng, Wen Chen, Jianwen Luo, Xinzhe Liu, Heng Yu, Yajun Ha (2021). -
Second Place, DAC 2020 System Design Contest
2020 Design Automation Conference
Weixiong Jiang, Xinzhe Liu, Hao Sun, Rui Li, Yajun Ha, Wen Chen, Shaobo Luo, Heng Yu (2020). -
Best Paper Award
2017 Proceedings of the Computing Frontiers Conference
Heng Yu, Yajun Ha, Jing Wang, “Quality Optimization of Resilient Applications under Temperature Constraints” (2017). -
Highlight Paper Award
2009 International Solid-State Circuits Conference (ISSCC) Y. Pu, J. Pineda, H. Corporaal, Y. Ha, “An Ultra Low-Energy/Frame Multi-standard JPEG Co-processor in 65nm CMOS with Sub/Near Threshold Power Supply” (San Francisco, USA, Feb. 2009). -
Best Poster Award
2008 19th ProRISC Workshop on Integrated System and Circuits
Veldhoven, Netherlands (2008). -
Best Paper Nomination
2007 17th International Conference on Field Programmable Logic and Applications (FPL)
Lee, W. Loke, W. Zhang, Y. Ha, “Fast and Accurate Interval-Based Timing Estimator for Variability-Aware FPGA Physical Synthesis Tools” (Amsterdam, the Netherlands, Aug. 2007).
Selected Publications
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Fast FPGA Accelerator of Graph Cut Algorithm With Threshold Global Relabel and Inertial PushIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2025
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RefSCAT: Formal Verification of Logic-Optimized Multipliers via Automated Reference Multiplier Generation and SCA-SAT SynergyIEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025
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eCIMC: A603.1-TOPS/W eDRAM-Based Cryogenic In-Memory Computing Accelerator Supporting Boolean/Convolutional OperationsIEEE J. Solid State Circuits, 2024
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A High-Throughput Full-Dataflow MobileNetv2 Accelerator on Edge FPGAIEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023
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AOS: An Automated Overclocking System for High-Performance CNN Accelerator Through Timing Delay Measurement on FPGAIEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023
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Criticality-Aware Negotiation-Driven Scrubbing Scheduling for Reliability Maximization in SRAM-Based FPGAsIEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023
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A Recursion and Lock Free GPU-Based Logic Rewriting Framework Exploiting Both Intranode and Internode ParallelismIEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023
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An Energy-Efficient Stream-Based FPGA Implementation of Feature Extraction Algorithm for LiDAR Point Clouds With Effective Local-SearchIEEE Trans. Circuits Syst. I Regul. Pap., 2023
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WDVR-RAM: A 0.25-1.2 V, 2.6-76 POPS/W Charge-Domain In-Memory-Computing Binarized CNN Accelerator for Dynamic AIoT WorkloadsIEEE Trans. Circuits Syst. I Regul. Pap., 2023
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HRFF: Hierarchical and Recursive Floorplanning Framework for NoC-Based Scalable Multidie FPGAsIEEE Trans. Circuits Syst. I Regul. Pap., 2023
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A Reliable and High-Speed 6T Compute-SRAM Design With Dual-Split-VDD Assist and Bitline Leakage CompensationIEEE Trans. Very Large Scale Integr. Syst., 2023
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A 40nm 0.35V 25MHz Half-Select Disturb-Free Bitinterleaving 10T SRAM With Data-Aware Write-PathIn IEEE Custom Integrated Circuits Conference, CICC 2023, San Antonio, TX, USA, April 23-26, 2023, 2023
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CIMC: A 603TOPS/W In-Memory-Computing C3T Macro with Boolean/Convolutional Operation for Cryogenic ComputingIn IEEE Custom Integrated Circuits Conference, CICC 2023, San Antonio, TX, USA, April 23-26, 2023, 2023
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Fast FPGA Accelerator of Graph Cut Algorithm with Out-of-order Parallel Execution in Folding Grid ArchitectureIn 60th ACM/IEEE Design Automation Conference, DAC 2023, San Francisco, CA, USA, July 9-13, 2023, 2023
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Ultra-Fast FPGA Implementation of Graph Cut Algorithm With Ripple Push and Early TerminationIEEE Trans. Circuits Syst. I Regul. Pap., 2022
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FODM: A Framework for Accurate Online Delay Measurement Supporting All Timing Paths in FPGAIEEE Trans. Very Large Scale Integr. Syst., 2022
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Hierarchical and Recursive Floorplanning Algorithm for NoC-Bascd Scalable Multi-Die FPGAsIn IEEE Asia Pacific Conference on Circuit and Systems, APCCAS 2022, Shenzhen, China, November 11-13, 2022, 2022
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DVFS-Based Quality Maximization for Adaptive Applications With Diminishing ReturnIEEE Trans. Computers, 2021