Digital  Integrated Circuits II (Spring 2017)


Lecture
  • Time:
    • Monday 1PM - 2:40PM
    • Wednesday 1PM - 2:40PM
  • Venue: SIST 1B-110.
  • Instructor:  周平强 <zhoupq@shanghaitech.edu.cn>
    • Office Hour: Tuesday 1PM-2PM.
  • TA: 李亚光<liyg@shanghaitech.edu.cn>
    • Office Hour: TBD.

Course Description

This course is targeted for students who have already taken basic VLSI design classes and would like to learn more about real world challenges in designing high-performance and low-power circuits. Lectures will emphasize on nanoscale CMOS issues such as leakage, variability, robustness, power delivery, interconnect, memory, etc.


 

 

References

  1. N. H. E. Weste and D. Harris, CMOS VLSI Design, 4th ed., Addison Wesley, Reading, MA, 2011.

  2. J. M. Rabaey, A. Chandrakasan, B. Nikolić, Digital Integrated Circuits - A Design Perspective, 2nd ed., 2003.

  3. J. Rabaey, Low Power Design Essentials, Springer 2009.

  4. A. Chandrakasan, W. Bowhill, F. Fox, Design of High-Performance Microprocessor Circuits, Wiley-IEEE, 2000.

 

Preliminary Materials for Guest Lecture Topics

  1. DFM (design for manufacturability)

    • Presentation by Andrew Khang at ICCAD 2003 [ppt]

    • Lecture notes by Sachin Sapatnekar at Univ. of Minnesota [pdf]

  2. Variability

    • K. Bernstein, et al, "High-performance CMOS variability in the 65-nm regime and beyond," IBM Journal on R&D, vol. 50, no. 4/5 2006. [pdf]

    • Shidhartha Das, "RAZOR: a variability-tolerant design methodology for low-power and robust computing". PhD thesis. Univ. of Michigan. [pdf]

    • Keith A. Bowman et. al., "Adaptive and resilient circuits for dynamic variation tolerance", IEEE Design & Test, vol. 30, no. 6, pp. 8-17, Dec. 2013. [pdf]

  3. Reliability

    • J. Fang et. al., “Circuit reliability: From physics to architectures,” ICCAD, pp. 243 – 246, 2012. [pdf]

  4. Thermal issues

    • Lecture notes by Sachin Sapatnekar at Univ. of Minnesota [pdf].

    • Lecture notes by Yuan Xie at Tsinghua University [pdf].

  5. 3D ICs

    • Lecture notes by  Yuan Xie at Tsinghua University [pdf1, pdf2].

  6. Near-Threshold Computing

    • R. Dreslinski et al, “Near-threshold computing: Reclaiming Moore’s Law through energy efficient integrated circuits,” Proceedings IEEE, Feb. 2010. [pdf]

    • H. Kaul et al, “Near-threshold voltage (NTV) design – opportunities and challenges,” DAC, June 2012. [pdf]

  7. Design for Testability

    • Lecture notes by Mark Horowitz at Stanford Univeristy. [pdf]

    • Lecture notes by Jacob A. Abraham at UT Austin. [pdf]

  8. Spintronic Logic and Memory

    • Keynote by Ian Young from Intel at Univ. of Minnesota. [pdf]

    • Tutorial by Yu Ma at ShanghaiTech Univ. [pdf]

  9. Hardware for Machine Learning

    • Tutorial by Honglak Lee at NIPS 2010. [pdf]

    • Lecture notes by Tony Martinez at Stanford University. Link: http://axon.cs.byu.edu/~martinez/classes/678/readings.html

    • Tutorial by William Dally at NIPS 2015. [pdf]

    • Tianshi Chen et. al., "DianNao: A Small-Footprint High-Throughput Accelerator for Ubiquitous Machine-Learning," ASPLOS, pp. 269 - 284, 2014. [pdf]

  10. Neuromorphic Chips

    • J. S. Seo et al., "A 45nm CMOS neuromorphic chip with a scalable architecture for learning in networks of spiking neurons," pp. 1-4, CICC, 2011. [pdf]

    • TrueNorth chip by IBM. [web, science paper, TCAD paper]

    11.

 

Course Schedule (Tentative)
Week Date
Topic
Reading
Lecture slides Assignments
1 Feb. 13 Introduction
  • Ref[1]: Chapter 1
  • Ref[2]: Chapter 1
  
Feb. 15    
2 Feb. 20 Design Flow
Feb. 22 Design Metrics  
3 Feb. 27 CMOS manufacturing  
Mar. 1 Lithography and advance CMOS process
  • Dennard scaling [pdf]
  • Experimental setup [pdf]
  • How to use Virtuoso [pdf]
  • HW1 [[pdf]
    • Due: March 8th, 1pm
  • Lab1 [pdf]
    • Due: March 8th, 1pm
  • Library files [tar file]
    •
4 Mar. 6 Device to circuit - overview  
Mar. 8 Transistor models
  • Ref[1]: Chapter 2
  • Ref[2]: Chapter 3
5 Mar. 13
Mar. 15
6 Mar. 20 Wire models
  • Ref[1]: Chapter 5
  • Ref[2]: Chapter 4
  
Mar. 22  
7 Mar. 27 CMOS Inverter
  • Ref[1]: Chapter 3, 4
  • Ref[2]: Chapter 5
  • HW2 [pdf]
    • Due: April 10th, 1pm
Mar. 29
8 April 3
April 5 Complex Logic
  • Ref[1]: Chapter 8
  • Ref[2]: Chapter 6
  • Lab2 [pdf]
    • Due: April 12th, 1pm
9 April 10  
April 12    
10 April 17
April 19
11 April 24  
April 26 Date Path
  • Ref[1]: Chapter 10
  • Ref[2]: Chapter 11
    
12 May 1  
May 3
  • HW3 [pdf]
    • Due: May 17th, 1pm
13 May 8  
  • Final project
    • Description [pdf]
    • Simulation files [download]
    • Deadline: May 21st for stage 1, June 4th for stage 2.
May 10  
14 May 15 Latches and Registers
  • Ref[1]: Chapter 9
  • Ref[2]: Chapter 7
  
May 17  
15 May 22 Timing and Clocks
  • Ref[1]: Chapter 9
  • Ref[2]: Chapter 10
  
May 24  
16 May 29        
May 31      
  • HW4 [pdf]
    • Due: June 7th, 1pm
17 June 5        
June 7 Memory
  • Ref[1]: Chapter 11
  • Ref[2]: Chapter 12