Typical MRAM bit cell consists of one transistor the as selector and one magnetic tunnel junction (MTJ) as the storage element. Although the memory performance mainly relies on MTJ, it is of importance to match the device performances between the transistor and MTJ. For example, the critical current density required to switch MTJ should falls in the driving capability of the transistor. In addition, the repeated read and write operations would not jeopardize the reliablity of transistor.

It is thus also necessary to examine whether such requirements can be fulfilled from the transistor side. In particular, we investigate the hot carrier degradation (HCD) of silicon on insulator (SOI) based MOSFETs that can be used as the driving transistor in MRAM bit cell. HCD is known as one of the major reliability issues in short channel devices, and the switching of MTJ would require the application of a high drain to source voltage that may aggravate HCD.

We are investigating two types of SOI MOSFETs with relatively novel device structures have been examined, i.e. double SOI (DSOI) and void embedded SOI (VESOI); and looking forward to develop more suitable SOI MOSFETs

References:
[1] Y. Qian et al., IEEE Trans. Electron Devices. 69, 5965 (2022)
[2] Y. Qian et al., IEEE J. Electron Devices Soc. 11, 319 (2023)